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Break it, Use it!

B. C. D. Core. Core. L1 Cache. L1 Cache. BlkState. BlkState. DirState. Break it, Use it!. L2 Cache. So what is MV5?. DRAM. GPU-like SIMD (SIMT) Hardware thread scheduler API for SIMD threads. Directory-based coherence (MESI, MSI). M5 based. On-chip Network (Mesh). A.

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Break it, Use it!

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  1. B C D Core Core L1 Cache L1 Cache BlkState BlkState DirState Break it, Use it! L2 Cache So what is MV5? DRAM GPU-like SIMD (SIMT) Hardware thread scheduler API for SIMD threads Directory-based coherence (MESI, MSI) M5 based On-chip Network (Mesh) A A / 11111111 B / 11111001 C / 00000110 Simulation Management for space exploration D / 11111111 Post-dominator time (b) Branch divergence and re-convergence (a) The example program Dual Core Tiled Cores OO+SIMD Note: SIMD cores can share the same address space with other cores over coherent caches! MV5: A RECONFIGURABLE SIMULATOR FOR HETEROGENEOUS MULTICORE ARCHITECTURESJiayuan Meng*, Kevin SkadronUniversity of Virginia * Now at Argonne National Laboratory Single-Instruction, Multiple-Threads Do you need it? Simulators for Today’s Architectures • If you want to explore: • SIMD + IO/OO • SIMD + coherent caches • SIMD + OCN • Simple Banked Cache • Underlying middleware • If you are OK with • System emulation • Kernels Out-of-Order (OO) core: SimpleScalar Simultaneous Multithreading: SMTSIM Chip-multiprocessor w/t OO cores: SESC Chip-multiprocessor w/t In-Order (IO), OO cores: Simics+Gems+Garnet, SimFlex Intel’s Microarchitecture: PTLSim GPU: GPGPUSim But Future is Unpredictable… Separate basic cache functionalities with coherence protocols General purpose / Heterogeneous / Integrated Accelerators? • Diversity • Modularity • Scalability • Co-design M5 provides such a platform MV5 is based on M5 Potential Configurations MESI/MSI SIMD OO On-chip Network In-order • MV5 Website • https://sites.google.com/site/mv5sim/home • MV5 Mailing list: • http://groups.google.com/group/mv5sim caches DRAM Acknowledgements This work was supported in part by SRC grant No. 1607, NSF grant nos. IIS-0612049 and CNS-0615277, a grant from Intel Research, and a professor partnership award from NVIDIA Research. We would like to thank Jeremy W. Sheaffer, David Tarjan, Shuai Che, and Jiawei Huang for their helpful inputs in power modeling, area estimation, and benchmark implementations.

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