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Computer Organization & Assembly Language

Computer Organization & Assembly Language

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Computer Organization & Assembly Language

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  1. Computer Organization & Assembly Language Instruction Execution Interrupts

  2. Instruction Cycle • Fetch • Fetch an instruction from memory • Decode the instruction to determine the operation • Fetch data from memory if necessary • Execute • Perform the operation on the data • Store the result in memory if needed

  3. Fetch instruction: CPU reads an instruction from memory. • Interpret instruction: instruction is decoded to determine what action is required. • Fetch data: execution of an instruction may require reading data from memory or an I/O module. • Process data: Execution of an instruction may require performing some arithmetic or logical operation on data. • Write data: Result of an execution may require writing data to memory or an I/O module.

  4. Computer Components – Top Level View

  5. Contd.. • CPU needs some internal memory • Internal CPU Registers: • Program Counter (PC) = Address of instruction • Instruction Register (IR) = Instruction being executed • Memory Address Register (MAR) = contains address of a location in memory • Memory Buffer Register (MBR) = contains a word of data to be written to memory or the word most recently read. • Accumulator (AC) = Temporary Storage

  6. Contd.. • Fetch the instruction from the memory • Address in the Program Counter register • Program Counter (PC) holds address of next instruction to fetch • Increment the Program Counter • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Decode the type of instruction • Fetch the operands • Execute the instruction • Store the results

  7. Characteristics of a Hypothetical Machine • Instruction (16 bit) • 4bits –opcode • 12 bits –address • 0001 = Load AC from memory • 0010 = Store AC to memory • 0101 = Add to AC from memory

  8. Example Program Execution

  9. Instruction Execution Cycle

  10. Instruction Cycle State Diagram

  11. Interrupts Changing Program Flow

  12. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error

  13. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

  14. Transfer of Control via Interrupts

  15. Instruction Cycle with Interrupts

  16. Instruction Cycle (with Interrupts) - State Diagram

  17. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt

  18. Multiple Interrupts - Sequential

  19. Multiple Interrupts – Nested

  20. Program Flow Control

  21. References • Chapter 1, Ytha Yu and Charles Marut, “Assembly Language Programming and Organization of IBM PC” • Chapter 3, William Stallings, “Computer Organization & Architecture”