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UART RX

TX Path. RX Path. UART. CheckSum. MessagePack Decoder. MessagePack Encoder. CheckSum. UART TX. UART RX. WBS. WBM. WBM. 3. A. D. Host ( Matlab ). WBM – Wishbone Master WBS – Wishbone Slave. Wishbone INTERCON. 1. WBS. Flash Component. FLASH. C. WBM. EGC Controller.

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UART RX

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  1. TX Path RX Path UART CheckSum MessagePack Decoder MessagePack Encoder CheckSum UART TX UART RX WBS WBM WBM 3 A D Host (Matlab) WBM– Wishbone Master WBS – Wishbone Slave Wishbone INTERCON 1 WBS Flash Component FLASH C WBM EGC Controller Flash FSM Flash Controller WBS Command Reg ECG FSM Aux Reg 2 RAM Reset en SPI CORE PHY FIFO FPGA ADS1298R ECG DB

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