1 / 12

TLM 2.0 Loosely Timed (LT) System Example - Simple

This document presents a simple implementation of TLM 2.0 in a loosely timed (LT) system using non-blocking options. It showcases the architectural principles behind the design, technical details of initiating and target modules, and provides annotated timing examples. The goal is to demonstrate the application of TLM 2.0 in real systems, enabling architectural exploration and early software development. Instructions for running the example on Linux and MSVC are included, along with expected outputs, making it a valuable resource for system designers and developers.

peers
Télécharger la présentation

TLM 2.0 Loosely Timed (LT) System Example - Simple

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. TLM 2.0 Loosely Timed (LT) System Example - Simple Jack Donovan, Anna Keist, Charles Wilson ESLX, Inc. June 2008

  2. AT System Example - Annotated Timing • The Goal is to Illustrate: • Application of TLM 2.0 in a real system • Annotated non-blocking (NB) option of the non-blocking style • NB annotated timing has been referred to as "1 phase" • Simplest version of non-blocking/AT • Possible Applications: • Architectural exploration • Early software development

  3. Example Block Diagram Router (SimpleBusLT) Initiator Module (initiator_top) Initiator Module (initiator_top) Target Module (lt_target) Target Module (at_1_phase_target) TLM 2 GP

  4. How to run this example (Linux) • SetSYSTEMC_HOME andTLM_HOME • cd examples/tlm/lt/build-unix • make clean • make • make run

  5. How to run this example (MSVC) • Open a explorer window onexamples/tlm/lt/build-windows • Launch lt.sln • Select ‘Property Manager’ from the ‘View’ menu • Under ‘lt > Debug | Win32’ select ‘systemc’ • Select ‘Properties’ from the ‘View’ menu • Select ‘User Macros’ under ‘Common Properties’ • Update the ‘SYSTEMC’ and ‘TLM’ entries and apply • Build and run

  6. Expected Output (expected.log) Info: lt_initiator.cpp: 80 ns - initiator_thread Initiator: 101 b_transport(GP, 0 s) Info: report.cpp: 80 ns - print ID: 201 COMMAND: WRITE Length: 04 Addr: 0x0000000000000004 Data: 0x00000004 Info: at_target_1_phase.cpp: 80 ns - b_transport Target: 201 returned delay of 0 s + 20 ns + 60 ns = 80 ns Info: lt_initiator.cpp: 80 ns - initiator_thread Initiator: 101 b_transport returned delay = 80 ns Info: lt_initiator.cpp: 80 ns - initiator_thread Initiator: 102 b_transport(GP, 0 s) Info: report.cpp: 80 ns - print ID: 201 COMMAND: WRITE Length: 04 Addr: 0x0000000000000004 Data: 0x00000004 Info: at_target_1_phase.cpp: 80 ns - b_transport Target: 201 returned delay of 0 s + 20 ns + 60 ns = 80 ns Info: lt_initiator.cpp: 80 ns - initiator_thread Initiator: 102 b_transport returned delay = 80 ns

  7. Initiator Module tlm_initiator_socket tlm_target_socket sc_export sc_port Initiator Module (initiator_top) Traffic Generator Module (traffic_generator) Request Queue (sc_fifo) Response Queue (sc_fifo) top_initiator_socket TLM Interface Module (lt_initiator)

  8. TLM Interface Module tlm_initiator_socket tlm_target_socket sc_export TLM Interface Module (lt_initiator) b_transport request_in_port simple_initiator_socket initiator_thread response_out_port sc_port

  9. Target Module (lt_target) tlm_initiator_socket tlm_target_socket sc_export sc_port Target Module (lt_target) memory_socket (simple_target_socket) memory b_transport

  10. Target Module (at_1_phase_target) tlm_initiator_socket tlm_target_socket sc_export sc_port Target Module (at_1_phase_target) memory_socket memory b_transport AT code

  11. Router Component Router Model (SimpleBusLT<2,2>) initiator sockets (2) target sockets (2) tlm_initiator_socket tlm_target_socket sc_export sc_port

  12. Expected Timing lt_target or at_1_phase_target lt_initiator b_transport(GP, delay)

More Related