1. Implementing multicore system using OpenRISC Advisor: MonyOrbach By: JehadGhanayem Ahmad Kiswani

2. Content • Background. • Working environment. • minSoC vs. orpSoC. • System configuration: • openRisc. • minSoC. • Simulation and synthesis. • Work schedule.

3. Background Project Goal: building a SoC based on a multicore implementation of the OpenRISC CPU. Term A Goal: building a SoC based on an OpenRISC CPU. • The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores. • The OR1200 design is an open source (under LGPL GNU) implementation of the OpenRISC 1000 RISC architecture.

4. Term A Primary Goal: building an OpenRISC based system on FPGA. • Configuring the CPU. • Building a SoC. • Simulation and Synthesis. • Implementation. • Debugging. • Benchmarking for future reference.

5. Working Environment • Windows • PlaneAhead (synthesis). • iMPACT (transferring design to FPGA). • Ubuntu • Icarus & or1ksim (simulation). • GTKwave (viewing waves created by Icarus). • GNU OpenRisctoolchain(or32-elf): • binutils, GCC and GDB (compilation and debugging). • newlib and uclibc (minimal C libraries). • And others …

6. FPGA used • XUPV5 Board

7. Choosing the SoC orpSoC minSoC • Developed by openCores. • More IP cores: • UART. • Ethernet. • VGA. • AC97… • Suitable for running linux. • More of a ready-design. • Developed by Raul Fajardo. • Minimal implementation: • UART • Ethernet, and that’s it. • Only the basics, meant to be configured. • simpler, but more advanced RAM model. • Easier to implement – at least on a virtex5 board.

8. Configuring minSoC

9. Configuring the OpenRisc CPU • 1-way set associative 4KB instruction and data cache. • No divide implementation (done by software). • Disabled DSP unit.

10. Simulation – workflow • The code is compiled with or32-elf-gcc. • The binary file is converted to a hex file. • The hex file is written into the memory HDL file. • The system is simulated using Icarus. • UART output is redirected to the terminal.

11. Simulation – the code

12. Simulation - results

13. Synthesis • Plenty of room for a multicore design.

14. Schematic

15. What’s Next • Exporting the design to the FPGA (2 weeks). • Testing the SoC (1 week). • Benchmarking (1 week). • Submitting a report (1 week). • Writing a script to automatically configure the system for XUPV5 board. • Writing the final report.

16. VirtualBox – again. • Linux operating system is essential to the project. • Root access is required. • VirtualBox: open source software under GNU GPL. allows the guest OS to run on virtual environment within the host OS. • VirtualBox Extension pack: allows the guest OS access to the USB. • Extra HD space: 10GB in total. • Virtualbox base image = 5GB • Virtualbox image with development tools = 8GB • 15% extra space

17. Thank you.