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Logic Design LAB 9

Logic Design LAB 9. 授課老師：伍紹勳 課程助教：邱麟凱、江長庭. Outline. Generate clock by IC 555 oscillator Implement count up counter by JK flip-flop 7476 JK flip-flop count up counter. Requirement.

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Logic Design LAB 9

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  1. Logic Design LAB 9 授課老師：伍紹勳課程助教：邱麟凱、江長庭

  2. Outline • Generate clock by IC 555 oscillator • Implement count up counter by JK flip-flop • 7476 JK flip-flop • count up counter

  3. Requirement • 220Ω電阻x 4 、7476 x 2、7400(NAND) x 1(buffer)、LED x 4、 7476 x 2、555x1、電阻470KΩx2(黃紫黃)、電解電容1μF x1

  4. 555oscillator • Refer to exp.11 555 Calculator (Website)

  5. 555oscillator • You can connect output of 555 to a buffer • Oscillator would be more stable • E.g. connect output of 555 to an inverter or AND output of 555 with signal 1 • Electrolytic capacitor(電解電容) • With polarity (long pin should connect to VCC) + -

  6. 7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs • Falling-edge Trigger JK Flip-Flop Preset Reset Toggle

  7. Count up counter 0000 20: 0->1 (Toggle) 0001 20: 1->0 (Toggle), carry to next digit 21: 0->1 (Toggle) 0010 20: 0->1 (Toggle) 0011 20: 1->0 (Toggle), carry to next digit 21: 1->0 (Toggle), carry to next digit 0100 22: 0->1 (Toggle)

  8. Count up counter • 4-bits output • output=input+1 at falling edge 0000 0001 1111 0010 0011 0100 +1 0101 1110 0110 1101 0111 1100 1011 1010 1001 1000

  9. Count up counter 題外話 : 在設計電路時，應盡可能遵守只用 ”單一時脈”及”不要把時脈拿來做邏輯運算”二個原則，以免產生不必要的Bug。(除非很有把握電路不會出錯)

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