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LHCb Outer Tracker Upgrade Actel FPGA based Architecture

LHCb Outer Tracker Upgrade Actel FPGA based Architecture. Outline Front end box Architecture Actel TDC Data GBT interface Data format Test Setup AMC40 test setup. Front-end box architecture. 17 januari 2013. Front-end box. 1 GBT master/power board (replaces: GOL board)

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LHCb Outer Tracker Upgrade Actel FPGA based Architecture

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  1. LHCb Outer Tracker UpgradeActel FPGA based Architecture • Outline • Front end box Architecture • Actel TDC • Data GBT interface • Data format • Test Setup • AMC40 test setup Antonio Pellegrino, Tom Sluijk, WilcoVink,

  2. Front-end box architecture 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  3. Front-end box • 1 GBT master/power board (replaces: GOL board) • Versatile link transceiver, <-> Master GBT • TFC signals • 1 SCA for monitoring (power, temperature, etc.) • 8 Optical data transmitters • 4 dual transmitters versatile link OR • 12-way optical transmitter, based on KK Ghan’svcsel driver (8+4 spare) • Power supplies based on CERN SM01C DC/DC conv. • 4 Actel TDC boards (replaces: OTIS boards) • 2 data transmitter GBT’s • Wide bus format data transmitters • One used for clocks, BxClkTpClk, TFC,clk • Spare clocks for TDC • 1 SCA • Actel re-programming via JTAG • GBT configuration • 4 Threshold DAC • Temperature monitoring • Soft reset Actel • 1 ActelPro-asic A3PE1500 • 32 channel, 5-bits TDC • Zero suppression • 8 ASDBLR boards (unchanged) 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  4. Actel TDC • Pro-Asic A3PE1500 (4 FPGA’s/FE-box) • 32 channel 5 bits TDC • Based on 4 320 MHz clocks(2 edges and 90phase shifted) • fixed placement (3 variants: top right bottom) • Zero suppression 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  5. Data GBT interface • Two options uses identical PCB, different Actel firmware • 8 Data GBT’s per FE-box • One ZS output bus per 16 channels • No bandwidth limitations • NZS full bandwidth readout possible • 4 data GBT’s per FE-box • One ZS output bus per 32 channels • Bandwidth limit, lower cost • Wide-bus GBT format 28b@160MHz 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  6. Two 16 ch. TDC in one FPGA Dual GBT’s 16 channel TDC Zero-supp 16 stages Fifo Readout GBT1 16 channel TDC Zero-supp 16 stages Fifo Readout GBT2 Actel FPGA Data Format (9 channels hit): GBT1 27 0 16 bits Hit pattern channel (0-15) 4 bits BX cnt 8 bits Status Padded ‘0’ 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Data Max 4 words when all channels are hit GBT2 16 bits Hit pattern channel (16-31) 4 bits BX cnt 8 bits Status Padded ‘0’ 5 bits Data 5 bits Data 5 bits Data 5 bits Data Max 4 words when all channels are hit 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  7. 32 channel TDC with single GBT 32 channel TDC Zero-supp 32 stages Fifo Readout GBT Actel FPGA Data Format (9 channels hit): GBT 27 0 16 bits Hit pattern channel (0-15) 4 bits BX cnt 8 bits Status Data 5 bits Data 5 bits Data 16 bits Hit pattern channel(16-31) 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Padded ‘0’ s 5 bits Dat Max 8 words when all channels are hit 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  8. OTTOv2 Test Setup • StratixIV 230 evaluation board • Dummy GBT, based on code Sophie baron • Not yet implemented • Small TFC • Data buffer (512MB DDR3) • I2C over Ethernet, dummy ECS/SCA • OTTDC to Optical: OTTOv2 • Prototype board with combined TDC board (OTIS) and Master GBTboard (GOL) • Actel TDC • Snap 12 optical receiver/transmitter • Versatile link: • Dual transmitter (data GBT) • Bi-directional (master GBT) • SM01C radiation hard DC/DC power converters • SCA Mezzanine (SCA pin-out not known) • Threshold DAC 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  9. Test setup 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  10. Test Setup Altera Dummy GBT slave Altera Dummy GBT master 1GbEth 1GbEth Snap12 Rx Snap12 Tx SCA Actel TDC Vers.Link Power ASDBLR left ASDBLR right 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  11. Test setup with AMC40 • OTTO with master/slave StratixIV • Data GBT emulated • Master GBT • TFC signals • ECS via E-Link to SCA • dev.brd as 1/4 Front end box • Needs GBT wide-bus FPGA code (S.Baron) • AMC40 used for DAQ and TFC/ECS • Needs AMC 40 firmware • TFC/ECS • OT data format, DAQ interface to 10GbE • PC control software available? • ECS/TFC (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) • DAQ->data-storage 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

  12. AMC40 test setup overview 17 januari 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,

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