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TDC in ACTEL FPGA continued

This document outlines the advancements in the Outer Tracker Upgrade, focusing on increasing the Time-to-Digital Converter (TDC) capacity to 16 channels. It describes essential connections to the GOL for enhanced data analysis, implementing a simple zero-suppress scheme. Critical tests will evaluate linearity and Differential Non-Linearity (DNL) at 40 MHz. The event data structure will include fine timing, hit patterns, and status flags. Preliminary simulations showcase success, setting the groundwork for comprehensive future testing.

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TDC in ACTEL FPGA continued

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  1. TDC in ACTEL FPGAcontinued Preliminary Tom Sluijk Hans Verkooijen Albert Zwart Fabian Jansen

  2. To be done • Increase the number of channels to 16. • Connect the TDC to a GOL to get better analyzing possibilities. • Tests: • Linearity • DNL • Temperature Outer Tracker Upgrade

  3. Test Setup Hit Inputs FPGA GOL TDC 16 channels Zero Suppress 96 bits @ 40 MHz 32 bits @ 40 MHz Outer Tracker Upgrade

  4. Zero Suppress • Simple zero-suppress scheme implemented now • If one hit in a Bx is valid, the data of all 16 channels is sent to the GOL. • The Event Data: • Header. • 64 bits Fine time (4 bits per channel). • Header: • Hitpattern (16 bits). • Bx counter. • Status Flags Outer Tracker Upgrade

  5. Compile Report • CORE Used: 2239 Total: 38400 (5.83%) • IO (W/ clocks) Used: 63 Total: 147 (42.86%) • Differential IO Used: 0 Total: 65 (0.00%) • GLOBAL (Chip+Quadrant) Used: 4 Total: 18 (22.22%) • PLL Used: 1 Total: 2 (50.00%) • RAM/FIFO Used: 48 Total: 60 (80.00%) • Low Static ICC Used: 0 Total: 1 (0.00%) • FlashROM Used: 0 Total: 1 (0.00%) • User JTAG Used: 0 Total: 1 (0.00%) Outer Tracker Upgrade

  6. Test Assembly Outer Tracker Upgrade

  7. Results up to now • Backannotated simulations are performed and it works fine. • No data taken yet. Outer Tracker Upgrade

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