Status of Actel FPGA evaluation tests by JAXA

1. Briefing: Independent NASA Test of RTSX-SU FPGAs Status ofActel FPGA evaluation tests by JAXA May 11, 2005 Noriko YAMADA Space Component Engineering Center Institute of Space Technology and Aeronautics Japan Aerospace Exploration Agency (JAXA) Note: notes were added to make clear device type and programming algorithm used. -- rk, editor

2. Table of Contents • Test Objectives • Test Samples • Test Vehicle • Equipment and Facilities • Interim Test Results • Summary • Future Plan Briefing: Independent NASA Test of RTSX-SU FPGAs

3. Test Objectives (1) MEC die devices - To determine the acceleration factors of the anti-fuse failures by performing long-term life tests at various temperatures with the maximum VCCA. (2) UMC die devices - To evaluate the reliability for space applications by performing long-term life tests and radiation tests. Briefing: Independent NASA Test of RTSX-SU FPGAs

4. Test Samples Note: MEC devices are programmed with the “old programming algorithm.” -- rk, editor Briefing: Independent NASA Test of RTSX-SU FPGAs

5. Test Vehicle (1) Design features 1- Maximum utilization of anti-fuses:  4-input AND-OR chains 2- Stable operation using an external clock circuit:  Easier failure detection 3- R-cells driven by skewed clock:  Delays detectable to less than 10nsec 4- Continuous monitoring of XORed outputs from the same circuit block:  Real-time detection of failures Briefing: Independent NASA Test of RTSX-SU FPGAs

6. Test Vehicle (2) Evaluation test circuit – Diagram x4:32A x8:72A Briefing: Independent NASA Test of RTSX-SU FPGAs

7. Test Vehicle (3) The number of antifuses in test vehicles Briefing: Independent NASA Test of RTSX-SU FPGAs Low and High were reversed, fixed -- rk, editor

8. Equipment and Facilities Test board – Main board Briefing: Independent NASA Test of RTSX-SU FPGAs

9. Interim Test Results (1): Test Items and Conditions Test items and conditions VCCA: 2.75VDC (including transient ripples) Briefing: Independent NASA Test of RTSX-SU FPGAs

10. 130 132 134 136 138 140 142 144 >145 Interim Test Results (2): Initial tPLH Distribution Initial tPLH distribution – A54SX32A (MEC, old programming algorithm) Initial tPLH distribution C3 80 C2 70 C1 C0 60 50 Frequency of Occurrence 40 30 20 10 0 tPLH [ns] Briefing: Independent NASA Test of RTSX-SU FPGAs

11. 140 120 100 80 60 40 20 0 Interim Test Results (3): Initial tPLH Distribution Initial tPLH distribution – A54SX72A (MEC, old programming algorithm) Initial tPLH distribution C7 C6 C5 C4 C3 C2 Frequency of Occurrence C1 C0 135 145 150 >155 140 tPLH [ns] unstable Briefing: Independent NASA Test of RTSX-SU FPGAs

12. Interim Test Results (4): Long-Term Life Long-term life test (A54SX32A): MEC, old programming algorithm 25 deg.C  Completed 827 Hours 7 failures / 27 devices 70 deg.C  Completed 741 Hours 3 failures / 27 devices 125 deg.C  Completed 689 Hours 2 failures / 27 devices Briefing: Independent NASA Test of RTSX-SU FPGAs

13. Interim Test Results (5): Long-Term Life Long-term life test (A54SX72A): MEC, old programming algorithm Completed 100 Hours 34 failures* / 77 devices * Without electrical test failures **16Hours later from 1st electrical test passed Briefing: Independent NASA Test of RTSX-SU FPGAs

14. Interim Test Results (6): Delta Delay Trend Delta delay trend – A54SX72A: MEC, old programming algorithm Delta tPD trend @5.0V after 100 hours Briefing: Independent NASA Test of RTSX-SU FPGAs

15. Interim Test Results (7): Delta Delay Distribution Delta delay distribution – A54SX72A: MEC, old programming algorithm Delta tPD distribution @5.0V after 100 hours Frequency of Occurrence 10 Delta Time (ns) Briefing: Independent NASA Test of RTSX-SU FPGAs

16. Interim Test Results (8): Weibull Distribution Weibull distribution (Preliminary : MEC, old programming algorithm) Failure was analyzed by Weibull for each circuit block. The data fitted very well with a linear equation, even from the early stage of testing. ITT B=0.16 h=8e9h B=0.11 h=6.47e10h B=0.065 h=7.81e20h Briefing: Independent NASA Test of RTSX-SU FPGAs

17. Interim Test Results (9): Failure Rate and FIT FIT rate:converted to 32A gate level (Preliminary: MEC, old programming algorithm) P(t) was calculated for each circuit block. FIT rate was calculated for each device. (i.e. 32A include 4 blocks, 72A include 8 blocks.) Briefing: Independent NASA Test of RTSX-SU FPGAs

18. Summary • The evaluation tests on MEC die devices started on March 18th, 2005 (A54SX32A, @tri-temperature; 25, 70, and 125deg.C) and on April 1st, 2005 (A54SX72A, @25deg.C). (2) Delays caused by anti-fuse degradation were observed and considered to be similar phenomena observed in tests conducted by ITT and NASA. Briefing: Independent NASA Test of RTSX-SU FPGAs

19. Summary (continued) • A preliminary Weibull fitting (MEC, old programming algorithm) parameter was calculated for each circuit block tentatively. 32A: b=0.065,h=7.81e20h 72A: b=0.11 ,h=6.47e10h (4) 32A equivalent FIT rate was calculated. 7.5M hours room temperature operation will be required for a preliminary analysis to achieve 100 FIT. Briefing: Independent NASA Test of RTSX-SU FPGAs

20. Summary (continued) (5) Data required for acceleration factor calculation are being collected. (6) The on-going long-term life tests will continue until they complete 1000 hours. Thermal cycling tests will follow each long-term life test. Radiation tests will be conducted on UMC die devices. Briefing: Independent NASA Test of RTSX-SU FPGAs

21. Future Plan Evaluation schedule Briefing: Independent NASA Test of RTSX-SU FPGAs