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ARM7 Microprocessor

ARM7 Microprocessor. Contents. System overview Introduction to ARM ARM7 Instruction Set Architecture ARM7 Microarchitecture. System. application. Code Density. Code Exe. Speed. OS & middleware. SW system. micro Processor. HW system. Memory system. Size. Power consumption.

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ARM7 Microprocessor

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  1. ARM7 Microprocessor

  2. Contents • System overview • Introduction to ARM • ARM7 Instruction Set Architecture • ARM7 Microarchitecture

  3. System application Code Density Code Exe. Speed OS & middleware SW system micro Processor HW system Memory system Size Power consumption peripherals Throughput controller

  4. Hardware/Software System Architecture

  5. Microprocessor • Factors in deciding processor architecture for a system • Operating environment • General purpose system • Special / limited purpose system (embedded system) • Required performance • Is high throughput required? (e.g. clock speed, pipeline depth) • Is optimized functionalities required? (e.g. communication) • Is power consumption control critical? • Tradeoffs • High performance = high power • Many functionalities = high power & size

  6. Microprocessor(cont’d) • High performance, general purpose Microprocessor • Processor Architecture & Performance • General purpose processors • Very high performance (e.g. throughput, clock speed, etc.) • Provide various functionalities (e.g. multimedia instruction set) • High throughput at cost of high power • Software vs. Hardware • Implementation overhead is in software • Software optimization is not critical • Examples • Intel Pentium class • AMD processors

  7. Microprocessor(cont’d) • Medium Performance, Embedded processors • Processor Architecture & performance • Embedded processors • Relatively high performance • Provided limited bus specialized functionalities (e.g. low power) • Architecture is decided by its main application environment • Software vs. Hardware • Implementation overhead is balanced between HW and SW • Hardware is optimized for a limited range of tasks • Software optimization in terms of hardware utilization is critical • Examples • ARMx processor • MIPSx processor

  8. Microprocessor(cont’d) • Low Performance, Cost-effective Processors • Processor Architecture & Performance • Low performance • Provide basic functionalities • Used in simple systems where cost is critical • Examples • 8051, 8086, 8088 • Motorola 68k series

  9. Contents • System overview • Introduction to ARM • ARM7 Instruction Set Architecture • ARM7 Microarchitecture

  10. ARM (Advanced Risc Machines) • Strength • High performance • Low price • Very low power consumption • Good development environment • Weakness • Lack of DSP operations • Opportunity • Mobile Computing Trend • Coming of Post-PC Age • Threat • Nothing at now

  11. Contents • System overview • Introduction to ARM • ARM7 Instruction Set Architecture • ARM7 Microarchitecture

  12. ARM processor overview • What is ARMx processor? • Designed by ARM(Advanced RISC Machine) • Standard 32-bit SoC pocessor(most widely used) • Balanced performance & size / power • ARM(T) Architecture • Support THUMB mode (16bit instruction) • Load-Store Architecture • Data processing operations only operate on register contents, not directly on memory contents • Powerful load & store instructions (e.g. indexing) • Conditional execution of all instructions (conditional flag) • Memory Mapped I/O • Four-word depth write buffer • Two-way set-associative, unified 8K-byte cache (instruction cache and data cache)

  13. load/store architecture • the access to memory is provided through a pair of dedicated instructions: • load - copy a value from memory into a register • store - copy a value from a register into memory • The alternative to load/store is found in CISC processors • offer a variety of addressing modes. With addressing modes, all instructions (for example arithmetic instructions) are able to use operands which are directly in memory. Since all of the operations can get directly to memory there is no need for special load and store instructions. • Elliminating the addressing modes is one of the ways that RISC processors are able to simplify the instruction set.

  14. ARM7 Programmer’s model • Overview • Operational Modes • Exceptions

  15. Overview • From the programmer’s point of view, the ARM can be in one of two states • Normal state: execute 32-bit, word-aligned ARM instructions • THUMB state: operate with 16-bit, half-word-aligned THUMB instructions • Transition between these two states does not affect the processor mode or the contents of the registers • THUMB instructions are one-half the bit width of normal ARM instructions • Produce very high-density codes • If the memory bus width is 16-bit or 8-bit, the THUMB instruction will be has a good performance than normal instruction sets

  16. Overview • Memory formats • View memory as a linear collection of bytes numbered upwards from zero • Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. • Can treat words in memory as being stored either in Big-Endian or Little-Endian format • Big-Endian format : the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte (byte 0 of the memory system is therefore connected to data lines 31 through 24) • Little-Endian format: the lowest numbered byte in a word is considered the word’s least significant byte, and the highest numbered byte the most significant. (byte 0 of the memory system is therefore connected to data lines 7 through 0)

  17. Little- and big-endian memory organizations If unaligned instruction fetches or data accesses will incur errors

  18. ARM7 Operational Modes • Table of ARM7 operational modes *User mode is subdivided into ARM and THUMB mode

  19. IRQ Mode • When the nIRQ signal asserts, the ARM chip changes to IRQ Mode

  20. FIQ Mode • When the nFIQ pin signal asserts, the ARM enters to the FIQ mode

  21. Supervisor mode • Reset or SWI instruction, the ARM enters to the Supervisor mode

  22. Abort Mode • Access an non-exist instruction or illegal memory address, the ARM enters to the Abort mode • The programmer can use BKPT instruction to enter Abort mode

  23. System mode and undefined mode • System mode • It is not entered by any exception • Intended for use by operating system tasks which need access to system resources • Use software to enter this mode • Undefined mode • ARM CPU tries to decode an illegal instruction then enter to the Undefined mode

  24. Register File Structure • The ARM processor has a total of 37 registers • General Purpose Register Files (GPR) • 31 general-purpose registers, including a program counter • These registers are 32 bits • Program Status Register Files (PSR) • 6 status registers • These registers are also 32 bits

  25. Register File Structure • Table of ARM7 general purpose register (GPR) file Purpose Register USR/SYS ABT UND SVC IRQ FIQ R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8 R9 R9 R9 R9 R9 R9 R9 R10 R10 R10 R10 R10 R10 R10 R11 R11 R11 R11 R11 R11 R11 R12 R12 R12 R12 R12 R12 R12 Stack Pointer R13 R13 R13 R13 R13 R13 R13 Link Register R14 R14 R14 R14 R14 R14 R14 PC R15 R15 R15 R15 R15 R15 R15

  26. ARM7 GPR (cont’d) • Visible register set • Registers that are visible during specific mode • 16x32bit registers are visible at any mode • Some registers are shared, some are not • Banked register • Registers that share the same index • Only 1 of banked registers are visible at each mode • R13(SP) and R14(LR) are banked • FIQ has 5 additional banked registers • Register dump overhead is reduced at context switch

  27. ARM7 GPR (cont’d) • Banked Register R13: Stack Pointer R13_USER R13_SVC R13 R13_ABORT R13_UNDEF Selector=CPSR

  28. ARM7 GPR (cont’d) USR/SYS ABT UND SVC IRQ FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 (PC)R15 CPSR SPSR Totally 37 registers, 18 registers are visible

  29. ARM7 GPR (cont’d) • R13, Stack pointer • Used when stack are implemented • Used when context switch occurs • Stores the stack pointer value of tasks • R14, Link Register • Used when mode change with return occurs • Stores the return address (current PC) • R15, Program Counter • Used to store current instruction address • A write to R15 is equivalent to branch instruction

  30. Instruction Pipeline • Three-stage pipeline is used • Fetch, Decoder, Execution • The program counter points to the instruction being fetch rather than to the instruction being execution • The Program Counter (PC) value used in an executing instruction is always two instructions ahead of the address

  31. The Relationship between pipeline and PC Normal ARM Mode

  32. The Relationship between pipeline and PC THUMB Mode

  33. Pipeline and return address

  34. Program Status Register Files (PSR) Register • Table of ARM7 program status register file USR/SYS ABT UND SVC IRQ FIQ CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR SPSR SPSR SPSR SPSR SPSR • CPSR • Stores current processor state • Contains condition flag and control bits • SPSR • Stores processor state before entering exception mode • Structure is identical to CPSR

  35. ARM7 PSR (cont’d) • ARM7 CPSR / SPSR Format

  36. ARM7 PSR (cont’d) • Control Bits I – Interrupt Mask bits (I, F) • Can be set or reset in privileged mode • If ‘1’, IRQ or FIQ requests are ignored • Control Bits II – THUMB Bit (T) • Must not be allocated by software • Is set or reset by H/W • If ‘1’, processor is running in THUMB state, else ARM state • Control Bits III – Mode Bits (M4 ~ M0) • Mode bits reflect current processor mode • Can be changed in privileged mode (results in mode change) • Is automatically changed in user mode by H/W

  37. Exceptions • Mode changes can be made under • Software control • External interrupts • Exception process • The modes other than user mode are privileged modes • Have full access to system resources • Can change mode freely • Exception modes • FIQ • IRQ • Supervisor mode • Abort: data abort and instruction prefetch abort • Undefined

  38. Exception Task flow Class Cause Interrupt External stimulus Fault Internal cause Trap Trap instruction

  39. Exception (cont’d) ARM7 (ISA v4) Exceptions Type Class Description (Cause) Reset Power Up Undefined Instruction FAULT Invalid / coprocessor instruction Prefetch Abort FAULT TLB miss for instruction Data Abort FAULT TLB miss for data access IRQ INTERRUPT Normal interrupt FIQ INTERRUPT Fast Interrupt (no context switch) SW Interrupt TRAP Undefined / coprocessor instruction

  40. Exception (cont’d) ARM7 (ISA v4) Exception Vectors Exception Address Mode on Entry Reset 0x00000000 Supervisor Undefined Instruction 0x00000004 Undefined SW Interrupt 0x00000008 Supervisor Prefetch Abort 0x0000000C Abort Data Abort 0x00000010 Abort IRQ 0x00000018 IRQ FIQ 0x0000001C FIQ Reserved 0x00000014 Reserved

  41. ARM Exceptions (cont’d) • On entry (automatically done by ARM) • 1) completes the current instruction (except reset exception) • 2) Changes to the operating mode corresponding to the 1) particular exception • 3) Saves the address of the following instruction in r14 of new mode • 4) Saves the old value of the CPSR in the SPSR of the new mode • 5) Disables IRQ exception; set bit 7 of the CPSR • 6) If it a FIQ exception, disable further FIQ; disables bit 6 of the CPSR • 7) Forces the PC to the address of exception handler

  42. ARM Exceptions (cont’d) • On exit • 1) Restores user registers • 2) Restores the CPSR using the SPSR • 3) set proper return address to PC • !! Conflict in performing step 2) and 3) • If step 2) is performed prior to step 3), then since lower bits of the CPSR determines the operating mode, restoring the CPSR makes it impossible to access the banked r14 • If step 3) is performed prior to step 2), exception handler loses the control and the code to perform step 2) is never accessed

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