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Simplified DPIM Testbench for Easy Debug and Verification

The DPIM Testbench provides a streamlined environment for debugging and verifying designs. It automatically instantiates the top module and leaves 7-segment signals unconnected, defines a clock signal, and initializes input signals with a reset. It supports register operations using the `write_reg()` and `read_reg()` functions, enabling efficient data manipulation, although it does not support file I/O. With a fixed clock period of 200 ns and short wait times, this testbench simplifies the process of writing and reading registers, ideal for FPGA projects.

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Simplified DPIM Testbench for Easy Debug and Verification

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  1. The DPIM Testbench Debug and Verification Made Easy!

  2. Features • Instantiates top (top.v) and leaves 7-seg signals unconnected • Defines a clock signal • Initializes input signals and generates a reset • Performs register write and read operations using write_reg() and read_reg() • Requires dpim_pkg.vhd for register operations • Does not support file I/O

  3. Write_reg() write_reg(1, X"0B", clk, astb, dstb, wr, db, pwait); • First argument is a decimal integer identifying which data register • Second argument is the data to be written in hexadecimal format • Other arguments are simply to make the handshake signals available to the write_reg() function

  4. Read_reg() read_reg(1, clk, astb, dstb, wr, db, pwait); • First argument identifies the data register • The retrieved data is driven on to the data bus until dstb goes high

  5. Gotchas! • Clock period is set at 200 ns • Only waits 20 clock cycles before reading. Does not check for “ready” • Response time to pwait is very short. That is, it doesn’t model the USB delay. • The testbench writes the address register on every byte transfer. That might not be true when using Adept for file I/O.

  6. Operations -- Write six bytes write_reg(1, X"0B", clk, astb, dstb, wr, db, pwait); write_reg(1, X"03", clk, astb, dstb, wr, db, pwait); write_reg(1, X"11", clk, astb, dstb, wr, db, pwait); write_reg(1, X"05", clk, astb, dstb, wr, db, pwait); write_reg(1, X"14", clk, astb, dstb, wr, db, pwait); write_reg(1, X"08", clk, astb, dstb, wr, db, pwait); -- Tell FPGA to process write_reg(0, X"01", clk, astb, dstb, wr, db, pwait); -- Should wait for ready light (ld7) wait for 20*cc; -- Read three results read_reg(1, clk, astb, dstb, wr, db, pwait); read_reg(1, clk, astb, dstb, wr, db, pwait); read_reg(1, clk, astb, dstb, wr, db, pwait);

  7. How to use • By default, Isim may run 1 us then stop. (You can change this under “properties”) • Restart the simulation (Blue back arrow) and add internal signals by highlighting “Inst_top” under “Tb” in “Instance and Process Window” • Then type “run all” to run through the entire testbench • Enjoy! 

  8. reg [(5*8):1] d_state; // Creates a bus that can hold five ASCII characters if (rst) d_state <= "pIDLE"; else case (d_state) […]

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