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Monday, November 29 Assignment(s) due: none

Monday, November 29 Assignment(s) due: none Please note: Next Monday is the cut-off for Assignments #11, #12 and #EC2 and for Quizzes #13 and #14 (extra credit) Thursday of this week is the cut-off for demonstrating and submitting your emulator

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Monday, November 29 Assignment(s) due: none

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  1. Monday, November 29 Assignment(s) due: none Please note: Next Monday is the cut-off for Assignments #11, #12 and #EC2 and for Quizzes #13 and #14 (extra credit) Thursday of this week is the cut-off for demonstrating and submitting your emulator Tonight is the cutoff for Assignments through #10, Quizzes through #12, and all optional quizzes left Practice exercises for the final are posted on the website

  2. A latch: - a circuit that will hold and store its values - adds a feedback loop to a circuit - output of each gate feeds back to the input of a previous gate gate #1 gate #2 - if D = 0 - the reverse process occurs - Q will be 0 - and the latch is reset to 0 - if D = 1 - output of gate #1 will be 0 (Q') - inputs to gate #2 will both be 0 - Q will be 1 and stay 1 - so the latch is set to 1

  3. - a clocked D-latch - the clock is normally 0 - keeps input to the NOR gates 0 (no matter what the value of D) - so the latch does not change state - when the clock is 1: - the latch is enabled - it responds to the value of D - input to gate 2 is always the complement of D gate #1 gate #2

  4. - a D flip-flop (a clocked D-latch with a gate delay) • - responds to input only when the clock is making the transition from low to high (or high to low) • - responds on the leading edge or the trailing edge of the clock pulse A gate delay

  5. Characteristic Table: - describes the state of a sequential circuit after 1 clock pulse for given inputs and given initial state - for the D flip-flop - only 1 input besides the clock Before the pulse After the pulse D(t)Q(t)Q(t+1) 0 0 0 0 1 0 1 0 1 1 1 1

  6. 3-bit memory (3 flip-flops) Data bus only used for a write operation Logic diagram for a 4 x 3 memory Each row is one 3-bit word. A read or write operation reads or writes a complete word. Decoder selects word (address bus) Chooses read or write operation (control bus) Control lines only used for a read operation Data bus

  7. Memory: - communication between the CPU and memory is handled by: - the address bus - the data bus - and the control bus - to read from memory - CPU puts the memory address on the address bus - and sets the control lines to read - then memory puts the data on the data bus - to write to memory - CPU puts data to be written on the data bus - and puts the memory address on the address bus - and sets the control lines to write

  8. CPU: - control unit - controls the fetch-decode-execute cycle - program counter and instruction register - data path of the computer - registers - arithmetic logic unit - operations are done in specific clock cycles - it takes four clock cycles to complete one data path cycle provide the interface between the control unit and the data path

  9. Clock Cycle 1: - data goes on to the A and B buses from the registers Clock Cycle 2: - data is moved to the A-latch and B-latch and held - control lines to the A- and B-latch are asserted only in this clock cycle Clock Cycle 3: - data in the A-latch and B-latch is stable - goes through the ALU and the shifter Clock Cycle 4: - data goes back to the registers and/or to the MBR

  10. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register

  11. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register Clock cycle 1: - A0 and B8 enable the A-bus and the B-bus - the PC contents are output to the A-bus - the ONE register contents are output to the B-bus

  12. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register Clock cycle 1: - A0 and B8 enable the A-bus and the B-bus - the PC contents are output to the A-bus - the ONE register contents are output to the B-bus Clock cycle 2: - the latches are enabled - data from the A-bus and B-bus is stored in the A-latch and B-latch

  13. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register Clock cycle 1: - A0 and B8 enable the A-bus and the B-bus - the PC contents are output to the A-bus - the ONE register contents are output to the B-bus Clock cycle 2: - the latches are enabled - data from the A-bus and B-bus is stored in the A-latch and B-latch Clock cycle 3: - contents of the latches are stable - the ALU adds the data from the latches - sends result through the shifter and on to the C-bus

  14. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register Clock cycle 1: - A0 and B8 enable the A-bus and the B-bus - the PC contents are output to the A-bus - the ONE register contents are output to the B-bus Clock cycle 2: - the latches are enabled - data from the A-bus and B-bus is stored in the A-latch and B-latch Clock cycle 3: - contents of the latches are stable - the ALU adds the data from the latches - sends result through the shifter and on to the C-bus Clock cycle 4: - data from the C-bus is stored back in the PC register

  15. To increment the program counter: - control lines enabled - A0: enables data from the PC register to output to the A-bus - B8: enables output from the ONE register to the B-bus - C0: enables output from the C-bus to the PC register Clock cycle 1: - A0 and B8 enable the A-bus and the B-bus - the PC contents are output to the A-bus - the ONE register contents are output to the B-bus Clock cycle 2: - the latches are enabled - data from the A-bus and B-bus is stored in the A-latch and B-latch Clock cycle 3: - contents of the latches are stable - the ALU adds the data from the latches - sends result through the shifter and on to the C-bus Clock cycle 4: - data from the C-bus is stored back in the PC register

  16. The microarchitecture level: - the control level of the SC - the level between the machine code instructions of the SC and the gates and circuits - the control unit determines the values on the 37 control lines - implemented as a microprogram stored in ROM - performs its own fetch-decode-and-execute cycle - the SC 20-field microinstruction is made up of - values of the control lines - simplified if possible - an address field for the address of the next microinstruction - a condition field - if the next microinstruction is the result of a jump - some fields of the microinstruction are binary - some fields are decimal

  17. tests decimal carry enables RMUX if 1, can store back in registers enables output no branch branch if negative branch if CF=TEST always branch (in microprogram) none right left rotate left address it will branch to (in microprogram) if condition is met no operation addition left input through 9’s complement of left The SC Microinstruction

  18. SC Control Store

  19. Clock Cycle 1: - MIR reads the microinstruction from the control store - the address is in the MPC - A and B fields output to the A-bus and B-bus decoders - appropriate registers output to the A and B buses

  20. Clock Cycle 1: - MIR reads the microinstruction from the control store - the address is in the MPC - A and B fields output to the A-bus and B-bus decoders - appropriate registers output to the A and B buses Clock cycle 2: - A-latch and B-latch are enabled - they are wired directly to the clock - they accept data from the buses - the data is stabilized

  21. Clock Cycle 3: (this is a busy cycle) - the S-latch is enabled - so the MPC is incremented - the MPC is held in the S-latch - if its line is asserted, the MAR reads data from the B-bus - data from the A and B buses go through the ALU and shifter to the C-bus, the carry and the RMUX - the COND1, COND2 and TEST fields of the MIR are evaluated

  22. Clock Cycle 3: (this is a busy cycle) - the S-latch is enabled - so the MPC is incremented - the MPC is held in the S-latch - if its line is asserted, the MAR reads data from the B-bus - data from the A and B buses go through the ALU and shifter to the C-bus, the carry and the RMUX - the COND1, COND2 and TEST fields of the MIR are evaluated Clock cycle 4: - the MPC receives either the incremented value or the address to jump to - the RMUX may output to the MBR - data on the C-bus may be stored back in a register . . . and we are ready to go again

  23. Microinstruction at Control Store address 0: (the MPC is initially 0) • The first part of the FETCH: • - puts the address in the PC in the MAR • - sets the instruction to READ Microinstruction 00: B is set to 0 (PC register) MAR control line is asserted RD control line is asserted

  24. Clock Cycle 1: - microinstruction 00 goes into the MIR - data in the PC register goes onto the B-bus [20] Clock Cycle 2: - A-latch and B-latch control lines are automatically asserted - data on the B-bus goes into the B-latch [20] Clock Cycle 3: - the address in the MPC is incremented and is held in the S-latch - the MIR’s condition fields are evaluated - data in the B-latch (address from the PC) goes to the MAR [20] - contents of the address in the MAR go onto the address bus [20] Clock Cycle 4: - the incremented address in the S-latch goes into the MPC (now 01) - the first microinstruction has started to read the SC instruction from memory

  25. Microinstruction at Control Store address 1: • The next part of the FETCH: • - increments the PC • - puts the instruction into the MBR Microinstruction 01: A is set to 0 (PC register) B is set to 8 (ONE register) ALU1 control line is asserted (01: add) ENC control line is asserted C is set to 0 (PC register) MBR control line is asserted RD control line is still asserted

  26. Clock Cycle 1: - microinstruction 01 goes into the MIR - data in the PC register goes onto the A-bus [20] - contents of the ONE register go onto the B-bus [001] Clock Cycle 2: - contents of the PC register go into the A-latch [20] - contents of the ONE register go into the B-latch [001] Clock Cycle 3: - the address in the MPC is incremented and is held in the S-latch (02) - contents of the A-latch and B-latch go into the ALU and are added [021] - data in the ALU goes to the shifter and carry and onto the C-bus [021] - data on the data bus from memory goes into the Rmux and to the MBR [040] Clock Cycle 4: - the incremented address in the S-latch goes into the MPC (now 02) - the contents of the C-bus goes to the PC register [21] • the second microinstruction puts the SC instruction from memory into the MBR and increments the PC

  27. Microinstruction at Control Store address 2: • The last part of the FETCH: • - puts the instruction in the IR Microinstruction 02: AMUX control line is asserted (accepted left bus) ALU2 control line is asserted (10: left bus through) ENC control line is asserted C is set to 1 (IR register)

  28. Clock Cycle 1: - microinstruction 02 goes into the MIR Clock Cycle 2: . . . Clock Cycle 3: - the address in the MPC is incremented and is held in the S-latch (03) - contents of the MBR go into the ALU, to the shifter and onto the C-bus [040] Clock Cycle 4: - the incremented address in the S-latch goes into the MPC (now 03) - the contents of the C-bus goes to the IR register [040] • the third microinstruction puts the SC instruction from memory into the IR, and the fetch is complete

  29. Microinstruction at Control Store address 3: • The first part of the DECODE: • - puts the address field of the instruction into the AMASK register • - tests for opcodes 5 through 9 Microinstruction 03: A is set to 1 (IR register) ALU2 control line is asserted (10: left bus through) ENC control line is asserted C is set to 6 (AMASK register) COND1 control line is asserted (01: branch if negative) ADDR is set to 09 (will branch if opcode is 5 ..9)

  30. Clock Cycle 1: - microinstruction 03 goes into the MIR - contents of the IR register go onto the A-bus [040] Clock Cycle 2: - contents of the A-bus go into the A-latch [040] Clock Cycle 3: - the address in the MPC is incremented and is held in the S-latch (04) - contents of the A-latch go into the ALU - N flag will be set if it’s 500 .. 999 (10’s complement) [negative flag not set] - contents of the ALU go to the shifter, the C-bus and the RMUX [040] - input to the MSL is tested [branch if negative] - the MSL outputs 0, so no branch Clock Cycle 4: - the incremented address in the S-latch goes into the MPC (now 04) - the contents of the C-bus goes to the AMASK register [40] - takes address field only - the fourth microinstruction puts the address field of the instruction into the AMASK register

  31. Microinstruction at Control Store address 4: • The next part of the DECODE: (opcode is 0 .. 4) • - tests for opcode 0 Microinstruction 04: A is set to 1 (IR register) ALU2 control line is asserted (10: left bus through) SH2 control line is asserted (10: shift left) ENC control line is asserted C is set to 3 (X register) TEST is set to 0 (for opcode 0) COND2 control line is asserted (10: branch if CF = TEST) ADDR is set to 64 (will branch if opcode is 0)

  32. Clock Cycle 1: - microinstruction 04 goes into the MIR - contents of the IR register go onto the A-bus [040] Clock Cycle 2: - contents of the A-bus go into the A-latch Clock Cycle 3: - the address in the MPC is incremented and is held in the S-latch (05) - contents of the A-latch go into the ALU and the shifter - does a shift left (if the instruction is 040, the CF is 0 and output is 400) - output from shifter goes to the C-bus and the RMUX [400] - input to the MSL is evaluated - the CF = TEST, so MMUX is enabled for the branch Clock Cycle 4: - the address field goes into the MPC (now 64) - the contents of the C-bus goes to the X register [400] - the fifth microinstruction tests for opcode 0 and branches to the code for INP if the condition is met - the sixth microinstruction tests for opcode 1, and so on

  33. Microinstructions for INPUT: - address for the input is in the AMASK register - these microinstructions would: - enable the MBR and IN control lines - read data from the input cards into the MBR - put the address in the AMASK register in the MAR - write the data from the MBR to the address in the MAR - transfer control to microinstruction 00 - and fetch the next SC instruction

  34. Microassembly language: - translated by a microassembler to generate the microinstructions stored in control memory SC microassembly language syntax: label: instruction; instruction; . . . ; instruction {comment}

  35. Microassembly language: - translated by a microassembler to generate the microinstructions stored in control memory SC microassembly language syntax: label: instruction; instruction; ...; instruction {comment} - an instruction can be - an assignment - assigns a value to a register or field e.g. mar := pc; pc := pc + one; ac := lshift (ac) - a branch e.g. goto FETCH; if C=3 goto SUB; - a field name - asserts a control line e.g. mbr; rd;

  36. Microassembly language: - translated by a microassembler to generate the microinstructions stored in control memory SC microassembly language syntax: label: instruction; instruction; ...; instruction {comment} - an instruction can be: - an assignment - assigns a value to a register or field e.g. mar := pc; pc := pc + one; ac := lshift (ac) - a branch e.g. goto FETCH; if C=3 goto SUB; - a field name - asserts a control line e.g. mbr; rd; - labels are used to identify sections of code for branching - labels and comments are optional

  37. SC microassembly language examples: - the fetch section: FETCH: mar := pc; rd; pc := pc + one; mbr; rd; ir := mbr; - the decode section DECODE: amask := ir; if N goto NEG; X := lshift (ir); if C = 0 goto INP; if C = 1 goto OUT; . . .

  38. The first three microinstructions are the fetch cycle: What is happening? The next instruction to be executed is fetched from memory and stored in the Instruction Register. The program counter is incremented. Step 1: The contents of the PC are output to the B bus and to the MAR Step 2: The contents of the PC are output to the A bus and the contents of the ONE register to the B bus. They are added in the ALU and the result is output to the C bus and stored in the PC register. The instruction at the memory address in the MAR is fetched from memory and placed in the MBR. Step 3: The instruction now in the MBR goes through the AMUX and the ALU to the C bus and to the IR.

  39. Microinstruction at Control Store address 0: (the MPC is initially 0) • The first part of the FETCH: • - puts the address in the PC in the MAR • - sets the instruction to READ Microinstruction 00: B is set to 0 (PC register) MAR control line is asserted RD control line is asserted FETCH: mar := pc; rd;

  40. Microinstruction at Control Store address 1: • The next part of the FETCH: • - increments the PC Microinstruction 01: A is set to 0 (PC register) B is set to 8 (ONE register) ALU1 control line is asserted (01: add) ENC control line is asserted C is set to 0 (PC register) MBR control line is asserted RD control line is still asserted pc := pc + one; mbr; rd;

  41. Microinstruction at Control Store address 2: • The last part of the FETCH: • - puts the instruction in the IR Microinstruction 02: AMUX control line is asserted (accepted left bus) ALU2 control line is asserted (10: left bus through) ENC control line is asserted C is set to 1 (IR register) ir := mbr;

  42. The next two microinstructions are the first part of the decode cycle: What is happening? The microprogram is identifying the opcode and setting up the branch to the part of the microprogram that handles the opcode. (The SC's ALU will set the Negative Flag if the value in the ALU is between 500 and 999.) Step 1: The instruction in the IR is copied to the AMASK register by way of the A bus, the ALU and the C bus. In the ALU the negative flag is set if the instruction is in the range 500 to 999. If the negative flag is set, the microprogram will branch to the second part of the decode section (at the label NEG). Step 2: The contents of the IR are output to the A bus, through the ALU to the shifter. The instruction is shifted left, leaving the opcode in the CF. If the CF = 0, the microprogram will branch to the label INP to execute the code that will input a number to memory from the input cards. (The next eight instructions will check the contents of the CF and branch to the appropriate code.)

  43. Microinstruction at Control Store address 3: • The first part of the DECODE: • - puts the address field of the instruction into the • AMASK register • - tests for opcodes 5 through 9 Microinstruction 03: A is set to 1 (IR register) ALU2 control line is asserted (10: left bus through) ENC control line is asserted C is set to 6 (AMASK register) COND1 control line is asserted (01: branch if negative) ADDR is set to 09 (will branch if opcode is 5 .. 9) DECODE: amask := ir; if N goto NEG;

  44. Microinstruction at Control Store address 4: • The next part of the DECODE: (opcode is 0 .. 4) • - tests for opcode 0 Microinstruction 04: A is set to 1 (IR register) ALU2 control line is asserted (10: left bus through) SH2 control line is asserted (10: shift left) ENC control line is asserted C is set to 3 (X register) TEST is set to 0 (for opcode 0) COND2 control line is asserted (10: branch if CF = TEST) ADDR is set to 64 (will branch if opcode is 0) x := lshift(ir); if C = 0 goto INP;

  45. If the microassembly instruction is X = amask; what path will it take through the datapath? - on to the A bus - through the ALU and the Shifter to the C bus - into the A register

  46. If the microassembly instruction is X = amask; what path will it take through the datapath? - on to the A bus - through the ALU and the Shifter to the C bus - into the X register What fields in the microinstruction must to be set to make this happen? - the A field - 6 (the AMASK register) - the ALU fields - 10 (left input through) - the Shifter fields - 00 (no operation) - the enc field - 1 (the C bus is enabled) - the C field - 3 (the X register)

  47. From Assignment #12: FETCH: mar :=pc; rd; pc := pc + 1; mbr; rd; ir := mbr; This is a read from memory (rd = 1). It will take 2 microinstructions to complete the read operation. The contents of the PC are output to the B bus (B = 0) and from the B bus to the MAR (mar = 1). The instruction at that memory location is sent to the MBR (mbr = 1). The contents of the PC output to the A bus (A = 0) and the contents of ONE to te B bus (B = 8). The ALU will add them (alu = 01) and output to the C bus. The C bus is enabled (enc = 1) and outputs back to the PC (C = 0). The contents of the MBR are output to the AMUX (amux = 1) and the ALU lets the data from the AMUX through (alu = 10). Contents of the ALU are output to the C bus, the C bus is enabled (enc = 1) and outputs to the IR (c = 1).

  48. The microinstruction at Control Store address 4 will test for opcode 0 If the opcode is in the Carry Flag, what field in the microinstruction need to be set to test for opcode 1? - the test field - TEST = 0 (for opcode 0) - the cond fields - the COND fields will be 10 (for branch if the CF = TEST) - the address fields - the ADDR fields will be 64 (the location of label INP, the code for opcode 0)

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