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Measurement Results on FEI4A CLKGEN: Analysis of Locking Time, Jitter, and Clock Response

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ritahenderson
31 diapositives · 343 Views · Jan 04, 2020

This study presents detailed measurements and analysis of locking time, jitter, and clock response of the FEI4A CLKGEN. Findings include locking time dependency on ICP, period jitter on 40MHz, clock cleansing factors, and more.

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Measurement Results on FEI4A CLKGEN: Analysis of Locking Time, Jitter, and Clock Response
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  1. Measurement Results on the FEI4A CLKGEN Kruth, T. Hemperek Feb. 2011

  2. Measurement Setup • Scope Tektronix TDS 5104B (1GHz/2.5GS/s) • Differential probes 1GHz • Pulse generator Agilent 81130A 400/660MHz • ICP prop. to change in amount of electrical charge on loop filter capacitor (DVctrl) per cycle • IBIAS default 128 • Bit order of biasing (ICP, IBias) has been corrected

  3. Locking Time and Range • Locking time depends on ICP • ICP=4, tLOCK=4.00us • ICP=16, tLOCK=1.25us • ICP=64, tLOCK=0.63us • Ref2Fast (yellow) and/or Fb2Fast (blue) „high“ indicate a re-lock of the CLKGEN • Input locking range 24MHz to 67MHz Lock acquired Blue – Fb2Fast Yellow – Ref2Fast

  4. Period Jitter on 40MHz • ICP set to 1 • Pulser (40MHz composed of two 20MHz signals?) • 40MHz CLKGEN output

  5. Jitter on 40MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 1, Ref2Fast high Cleansing Factor 4! Screenshot of scope jitter software

  6. Jitter on 40MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 4 Change in the results is not significant Screenshot of scope jitter software

  7. Jitter on 40MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 64 4ps change is within measurement accuracy Screenshot of scope jitter software

  8. Jitter on 160MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 4 4ps change is within measurement accuracy Screenshot of scope jitter software

  9. Jitter on 40MHz CLKGEN Output vs. IBIAS • Ch3 – CLKGEN, Ch4 – Pulser, ICP=4 • Different settings of IBias have no effect on jitter IBias 16 254 • !!! Different Ibias !!! Screenshot of scope jitter software

  10. 160MHz: Jitter on Reference with different Outputs enabled 160MHz enabled 40MHz, 80MHz, 160MHz enabled 40MHz, 160MHz, 320MHz enabled all enabled Basically no change on CLKGEN output

  11. CLKGEN Response to bad Reference Clocks • Every Second edge of reference clock delayed 4 ns • Green = reference clock, pink = CLKGEN output

  12. Clock Recovery from bad Reference Clock • ICP=1, periode time histogram, TNOM=25 ns • Every second edge of reference clock delayed by 4ns • CLKGEN output 40MHz Histograms of measured clock periods

  13. Jitter on 160MHz CLKGEN Output with a bad Reference Clock • Ch3 – CLKGEN, Ch4 – Pulser, ICP =4, Dt=5ns Cleansing ns to ps Screenshot of scope jitter software

  14. Probe Connection to PCB • Differential Probe conntected directly with adapter The Probe adpater seems to filter some jitter

  15. CLKGEN DC Power Consumption • All Enables = 0 • with JVDDPLL jumper 3 mA @VDDD1 • w/o JVDDPLL jumper 1 mA @VDDD1 • => CLKGEN basically off 2 mA • ENPLL=1, EN160M=1, rest of EN =0 • with JVDDPLL jumper 4 mA @ VDDD1 • w/o JVDDPLL jumper 1..2 mA @VDDD1 • => CLKGEN working 2..3 mA

  16. Conclusion • CLKGEN operational • CLKGEN input locking range (24..67 MHz) • Higher ICP reduces locking time (minor importance) • ICP bias current should be set low (e.g. ICP=4..16) for low jitter output clock signal • Stable jitter performance for a wide range of IBias setting • Cleansing of dirty reference input clock oberserved at CLKGEN output

  17. Thanks for your attention!

  18. Appendix

  19. Jitter on 160MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 1 Screenshot of scope jitter software

  20. Jitter on 320MHz CLKGEN Output • Ch3 – CLKGEN, Ch4 – Pulser, ICP set to 4 ??? Screenshot of scope jitter software

  21. 40MHz: Jitter on Reference with different Outputs enabled Only 40MHz enabled 40MHz, 80MHz enabled Only 160MHz disabled all enabled Basically no change on CLKGEN output Reference Jitter changes ?

  22. Timing Jitter for different Clocks • Timing jitter is almost constant • The reference signal seems worse when the 160 MHz output is enabled

  23. Jitter on 40MHz CLKGEN Output with a bad Reference Clock • Ch3 – CLKGEN, Ch4 – Pulser, ICP =1, Dt=4ns Cleansing ns to ps Screenshot of scope jitter software

  24. Jitter on 160MHz CLKGEN Output with a bad Reference Clock • Ch3 – CLKGEN, Ch4 – Pulser, ICP =4, Dt=0.5ns Cleansing ns to ps Screenshot of scope jitter software

  25. Jitter on 160MHz CLKGEN Output with a bad Reference Clock • Ch3 – CLKGEN, Ch4 – Pulser, ICP =4, Dt=10ns Cleansing ns to ps Screenshot of scope jitter software

  26. The following slides contain manually written tables • The values have been manually read from the scope screen and not from the scope jitter software module • The values were fluctuating • I tried to pick pessimistic values

  27. Cleansing of 40 MHz Clock • Delay of reference edges Dt=4ns

  28. Cleansing of 40 MHz Clock • Delay of reference edges Dt=3ns

  29. Cleansing of 40 MHz Clock • Delay of reference edges Dt=2ns

  30. Cleansing of 40 MHz Clock • Delay of reference edges Dt=0ns

  31. Cleansing of 160 MHz Clock • Delay of reference edges Dt=2.5ns • Values manually obtained and not with scope jitter software