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CRU Weekly Meeting

Evaluation of 10G PON downlink system using Original LHC Clock and LTU CRU for deterministic data transfer with low jitter and phase relations between clock points. CRU clocking scheme utilizing Arria 10 FPGA.

robertjenkins
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CRU Weekly Meeting

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  1. CRU Weekly Meeting Erno DAVID, Tivadar KISSWigner Research Center for Physics (HU) 13 January, 2016

  2. 10G PON Downlink Evaluation Original LHC Clock LTU CRU 9.6 Gbps 1 1 Source Payload bits Recovered LHC Clock 2 Optional measurement point in the middle 2 Payload bits Recovered LHC Clock GBTx ASIC 4.8 Gbps 3 Destination 3 Payload bits • Our goal is to deliver the LHC clock and the payload bits from point 1 to 3 with: • Deterministic phase relations between the source and destination clock after each power cycle • Low jitter • Deterministic delay regarding the payload bits expressed in clock cycles 2

  3. CRU Clocking Scheme CRU Arria 10 FPGA 240MHz 10G PON Transceiver TTS Gear Box 10G PON REFCLK 240MHz 40MHz External PLL + Jitter Cleaner 192 bit TTS_RX_CLK 240 MHz 7 0 3 120MHz 40MHz GBT Transceiver Bank 0 GBT Gear Box TPC Specific User Logic SAMPA readout controls,SAMPA packet decoders, Cluster Finder, Safety Monitoring System PCIe Endpoint 0 PCIE_0_REFCLK 100 MHz 120MHz 40MHz GBT_BANK_0_REFCLK 120 MHz 250MHz 80 bit PCIe DMA 256 bit PCIe Endpoint 1 PCIE_0_REFCLK 100 MHz 120MHz 40MHz GBT Transceiver Bank 3 GBT Gear Box 250MHz 120MHz 40MHz PCIe DMA GBT_BANK_3_REFCLK 120 MHz 256 bit 80 bit GBT-SCA PCIe BAR Rd/Wr PCIe 0 BAR xMM-Master GBTx Avalon-MM Bus (64 bit @ 100 MHz) 3

  4. LHC Clock Distribution CRU PON Frame 6x40 bits @ 40 MHz 9.6 PON Downlink LTU K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 . . . PON Receiver 40 bit 40 bit LHC clock (40 MHz) PON RX clock (240 MHz) PON TX clock (240 MHz) 1 Reconstructed LHC clock (40 MHz) 2 GBT REF clock (120 MHz) 3 GBT TX clock (120 MHz) GBT Frame 3x40 bits @ 40 MHz 4.8 GBT Downlink GBTX H H H H H H GBT Transmitter Reconstructed LHC clock (40 MHz)

  5. 10G PON Downlink Reference Design (Kintex 7) 9.6 Gbps Kintex 7 Kintex 7 ONU Recovered LHC Clock OLT Original LHC Clock GTX GTX AXI AXI MicroBlaze MicroBlaze Ethernet Link Ethernet Link Remote Terminal Remote Terminal 5

  6. 10G PON Downlink Evaluation Project External 10G PON Downlink FPGA 10G PON Transceiver or Glue Logic for internal parallel connection OLT ONU Original LHC Clock 240 MHz 240 MHz Recovered LHC Clock 32 bit 40 bit Payload bits LHC Clock 240 MHz AXI AXI Phase Monitoring QSYS Interconnect Avalon-MM Master (JTAG-to-Avalon-MM) Avalon-MM Master (JTAG-to-Avalon-MM) System-Console(TCL test script) 6

  7. Git Repository: 10gpon_eval 10gpon_eval ├───sim │ ├───olt │ ├───onu │ └───top ├───src │ └───modules │ ├───olt │ ├───onu │ └───qsys │ └───olt_onu └───syn ├───a10gx-devkit │ └───src ├───de0-nano │ └───src │ ├───constraints │ └───modules │ └───top ├───mini-daq │ └───src └───pcie40 └───src • Ability to simulate and synthesize on different levels • parallel 40 bit connection between OLT and ONU (single FPGA) • serial loopback connection between OLT and ONU (single FPGA) • external 10G PON donwlink • User interface will be based around System Console Dashboard – this would allow a standalone mode (outside of PC) • Only relevant source code is stored in the git repository • Buildable from command line • GitLab URL: https://gitlab.cern.ch/alice-cru/10gpon_eval 7

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