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Yoon-Jong Lee Sr. Manager Device Engineering Team

SPICE Model. Yoon-Jong Lee Sr. Manager Device Engineering Team. Contents. 1. SPICE Model - Quality Assurance - 0.25um SPICE Model (aa2533C07.A) - 0.21um SPICE Model (aa1833C07.0) 2. Statistical Modeling 3. Interconnect Capacitance 4. Mixed Signal Characterization

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Yoon-Jong Lee Sr. Manager Device Engineering Team

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  1. SPICE Model Yoon-Jong Lee Sr. Manager Device Engineering Team

  2. Contents 1. SPICE Model - Quality Assurance - 0.25um SPICE Model (aa2533C07.A) - 0.21um SPICE Model (aa1833C07.0) 2. Statistical Modeling 3. Interconnect Capacitance 4. Mixed Signal Characterization 5. TCAD Simulation

  3. Short Channel, Narrow Width Effects Non-Uniform Doping Effect Drain Induced Barrier Lowering Mobility Reduction with Gate and Substrate Bias Parasitic Source/Drain Resistance Better Fitting Accuracy at Near- Threshold Region for Analog Simulation Anam SPICE Model (Modeling from -55C to 150C) Device sizes for modeling (aa2533C07.A) BSIM3v3.1

  4. Quality Assurance of SPICE Model

  5. 0.25um SPICE Model (aa2533C07.A) NMOS Ids-Vds 11.98/0.25 VB=0V T=27C PMOS Ids-Vds 11.98/0.25 VB=0V T=27C PMOS Ids-Vgs 11.98/0.25 VD=-0.1V T=27C NMOS Ids-Vgs 11.98/0.25 VD=0.1V T=27C

  6. 0.21um SPICE Model (aa1833C07.0) PMOS Ids-Vds 16.6/0.21 VB=0V T=27 NMOS Ids-Vds 16.6/0.21 VB=0V T=27 PMOS Ids-Vgs 16.6/0.21 VB=-0.1V T=27 NMOS Ids-Vgs 16.6/0.21 VD=0.1V T=27

  7. Threshold voltage vs. Gate length NMOS PMOS aa2533C07.A w/o Pocket NMOS PMOS aa1833C07.0 with Pocket

  8. Temperature Characteristics of IDSAT NMOS Vdd=2.8V VB=0V PMOS Vdd=-2.8V VB=0V aa2533C07.A NMOS Vdd=2V VB=0V PMOS Vdd=-2V VB=0V aa1833C07.0

  9. Gate Delay Time vs. Supply Voltage (aa2533C07.A)

  10. Gate Delay Time vs. Temperature (aa1833C07.0) NMOS = 0.5/0.21um PMOS = 0.8/0.21um Fanout = 1

  11. Process Parameter Distribution Mean=44.6 S. Dev. =0.36 Mean = 0.541 S. Dev.= 0.022 Mean = 43.5 S. Dev.= 0.37 Mean = -0.510 S. Dev.= 0.024

  12. 240 FF 220 2σ SF 200 3σ IdsatP (uA/um) 180 FS TT 160 SS 140 420 440 460 480 500 520 540 IdsatN (uA/um) Sigma Contour Plot of 10/0.21um Device (aa1833C07.0)

  13. Interconnect Capacitance

  14. Ring Oscillator with Capacitance Loading Schematic of Test Pattern Metal 2 Line Wp/Lp=10/0.24 Wn/Ln=5/0.24 Metal 1 & 3 Plate Unit : [um]

  15. Gate Delay Time vs. Supply Voltage (aa2533C07.A)

  16. Mixed signal resistors ● aa2533C07.A

  17. Mixed signal capacitors ● aa2533C07.A * Target value

  18. MOSFET mismatch - aa2533C07.A Mismatch σ＝ A /√(W×L) ( W : Gate width , L : Gate length )

  19. Parasitic pnp bipolar characteristics - aa2533C07.A Emitter size : 1 × 1 [um]

  20. TCAD Simulation SIMS Profile Calibration IChannel & Well Profile (Boron)

  21. TCAD Simulation SIMS Profile Calibration IIMDD Profile (Arsenic)

  22. TCAD Simulation SIMS Profile Calibration IIIS/D Profile (Arsenic & Phosphorous)

  23. TCAD Simulation Simulated & Measured I-V Characteristics Ids vs. Vds of 0.21㎛ NMOS Ids vs. Vgs of 0.21㎛ NMOS

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