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ITRS Roadmap Design Process Open Discussion EDP 2001

ITRS Roadmap Design Process Open Discussion EDP 2001. Donald Cottrell Si2, Inc. Technology Trend - The Big. Designer Productivity. Transistors per Month. Year. Technology Trend - The Bad. % Mixed Signal. %. Year. Diversity. Technology Trend - The Ugly. Mutual Coupling Noise Coupled

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ITRS Roadmap Design Process Open Discussion EDP 2001

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  1. ITRS RoadmapDesign ProcessOpen DiscussionEDP 2001 Donald Cottrell Si2, Inc. EDP '2001

  2. Technology Trend - The Big Designer Productivity Transistors per Month Year EDP '2001

  3. Technology Trend - The Bad % Mixed Signal % Year Diversity EDP '2001

  4. Technology Trend - The Ugly • Mutual Coupling • Noise • Coupled • External • Power • di/dt • IR Drops • Electromigration • High Frequency • Transmission lines • Reflections EDP '2001

  5. Breaking Down the “Walls” Digital Analog Software Architecture RTL Synthesis FloorPlan Layout Checking Mask Prep Manufacture EDP '2001

  6. Magma’s single unified data model enablesa correct-by-construction design flow. Breaking Down the “Walls” EDP '2001

  7. 1 ASCII 2 ASCII ASCII ASCII MW Genesis 3 ASCII ASCII EDA Evolution - 2001 EDP '2001

  8. Reality • No external vendor meets all IC design needs, All EDA vendors together don’t meet all needs. • Nearly impossible for startups to break into the business dueto integration barriers, Startups enter business with intent to be purchased, BUT once purchased by “big guys”, a time lag and loss of innovation result. • Industry partnerships provide value, BUT integration acts as a barrier. EDP '2001

  9. All or Nothing at All EDP '2001

  10. CorelDraw Access Lotus123 FrameMaker The Need - Customer Choice EDP '2001

  11. Fire&Ice Customize Solution to Fit the Need Calibre SE Mars-XTalk EDP '2001

  12. 1 ASCII 2 ASCII ASCII ASCII MW Genesis 3 ASCII ASCII A Better Model Open Model and API 4 EDP '2001

  13. EDA System Needs Architectural Architectural • High Performance integration and tools:Architecture and Assembly Function, Performance, Power, ..RTL through Mask design and analysis • Constraint driven design tools (power, timing, signal integrity, …) • Integration via Open Architecture Industry-standard data model Industry-standard API • Incremental analysis and optimization • Concurrent design and analysis • Common Calculation Engines • Abstracted Model BuildersIndustry Standard interfaces Design Calculation Engines Design Cell and Core Library Delay Delay Power RTL RTL Function Extraction Design Properties Design Cell Geometry Abstract Synthesis Synthesis Detailed Process Lib Floor Plan Floor Plan Substrate Dielectric Metal Place&Route Place&Route Via Incremental Incremental Design API Industry Standard Extraction Extraction Final Final Signoff Signoff Verification Verification Test Generation Database EDP '2001

  14. Standards vs. Innovation • Did SQL hurt Relational Database sales? • Did MAC grow faster than PC? • Are we happy with the rate of university research technology transfer? • Is there a better way to do cooperative design? SoC? • Can we continue with ASCII file exchange vs. true interoperability? EDP '2001

  15. P ASIC Complexity Return COTS Discussion • Do we really need an Open Infrastructure? • Will an EDA MicroSoft emerge - Is that bad? • Can an EDA Linux model work? • Does one-size fit all? • Analog/RF/MEMS • ASIC (compiled HDL --> gates) • High-volume custom (uP, DSP, embedded memory, reprogrammable) • SOC (high integration, low cost, low TTM) • Memory • Are product markets significant? • Portable & Wireless, Broadband, Internet Switching, Mass Storage, Consumer, Computer, Automotive • Can we develop the necessary metrics? EDP '2001

  16. Market Drivers EDP '2001

  17. Market Drivers EDP '2001

  18. 1997 NTRS EDP '2001

  19. 1999 ITRS EDP '2001

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