FIGURE 3–4 Simple implementation of a logic AND operation

FIGURE 3–1 8051 Addressing modes. (a) Register addressing (b) Direct addressing (c Indirect addressing (d) Immediate addressing (e) Relative addressing (f) Absolute addressing (g) Long addressing (h) Indexed addressing

FIGURE 3–2 Calculating the offset for relative addressing. (a) Short jump ahead in memory (b) Short jump back in memory

FIGURE 3–3 Instruction encoding for absolute addressing. (a) Memory map showing 2K pages (b) Within any 2K page, the upper five address bits are the same for the source and destination addresses. The lower 11 bits of the destination are supplied in the instruction

FIGURE 3–4 Simple implementation of a logic AND operation

FIGURE 3–5 Instruction sequence for worst-case propagation delay

FIGURE 3–6 Logic gate programming problems. (a) 3-input NOR. (b) 8-input NADD. (c 3-gate logic operation.

FIGURE 3–7 Logic gate programming problems. (a) 2-gate logic circuit. (b) 3-gate logic circuit. (c) 4-input NOR.

FIGURE 3–8 Interface to a DIP switch and 7-segment LED

FIGURE 3–4 Simple implementation of a logic AND operation