ITRS Conference April 19 and 20 Stresa Italy 2004 ITRSYield Enhancement (YE) Update Ines Thurner
Yield Enhancement TWG Participants : Kevin Pate Intel, Chris Muller Purafil, Masahiko Ikeno Renesas, Dieter Rathei AMS, M.Retersdorf AMD, A. Neuber M + W Zander, A. Nutsch Fraunhofer IISB , L. Pfitzner Fraunhofer IISB, Ines Thurner Infineon
YE Difficult Challenges • High-Aspect-Ratio Inspection. • High-speed, cost-effective tools are needed to rapidly detect defects at 1/2 X ground rule (GR) associated with high-aspect-ratio contacts, vias, and trenches and especially defects near or at the bottoms of these features. • Design for Manufacture & Test (DFM & DFT) • IC designs must be optimized for a given process capability and must be testable and diagnosable • Correlation of Impurity Level to Yield. • Data, test structures and methods are needed for correlating process fluid contamination types and levels to yield and determine required control limits • Data Management and Test Structures for Rapid Yield Learning. • Automated, intelligent structures, analysis and reduction algorithms that correlate facility, design, process, test, and work-in-process (WIP) data must be developed to enable the rapid root-cause analysis of yield-limiting conditions.
YE Difficult Challenges (continue) • Yield Models • Random, systematic, parametric, and memory redundancy models must be developed and validated to correlate process-induced defects (PID), particle counts per wafer pass (PWP), and in-situ tool/process measurements to yield. • Systematic Mechanisms Limited Yield (SMLY) • Understanding SMLY is mandatory for achieving historic yield ramps in the future. • Non-visual Defect Detection • In-line and end-of-line tools and techniques are needed to detect non-visual defects.
YE – focus 2004/2005 • Relative importance of different contaminants to wafer yield • Continue validation of contamination targets thru benchmarking • New defect budget survey to correct or validate defect budgets for process tools and improve yield model • Integrate test structure in yield learning subtopic • Wafer inspection of backside, bevel, edge, nanotopographie and geometry