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Totem Collaboration meeting

Totem Collaboration meeting. Saverio Minutoli INFN Genova 27 September 2006. T1status overview: Electronic cards AFEC – CFEC VFAT emulator mezzanines. Cabling Fibers H.V. T1 electronics system. DOHM-CCU SLOW CONTROL RING. CSC Plane_n+1. 6xCFEC = 2x192chs. AFEC 220chs. 50cm.

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Totem Collaboration meeting

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  1. Totem Collaboration meeting Saverio Minutoli INFN Genova 27 September 2006 • T1status overview: • Electronic cards • AFEC – CFEC • VFAT emulator mezzanines • Cabling • Fibers • H.V.

  2. T1 electronics system DOHM-CCU SLOW CONTROL RING CSC Plane_n+1 6xCFEC = 2x192chs AFEC 220chs 50cm CSC Plane_n • boards shielded with faraday cages.

  3. Adapted to the CSC plane type 5P We have had some problem with the first design New PCB Design almost completed. Major modifications: Shielding – cross talk – lines length equalization Ready to produce the prototype next week. Components procurement completed. Pcb production need 2 weeks Components loading 1 week Ready to mount on the CSC-5P, end of October Anode Front End Card (1)

  4. AFEC (2) • Layout first prototype top bottom

  5. Design completed. PCB prototypes produced. Components procurement completed. Ready to load the components on the boards: External firm This week, mounting tools production. Next week we will have the board on the desk. CFEC (1)

  6. CFEC LAYOUT - TOP

  7. CFEC (2)

  8. CFEC (3) with VFAT digital emulator with VFAT digital

  9. CFEC box (4) • Shielding • Heat dissipation

  10. CFEC 2nd version (5) Cathode with VFAT analog Cathode signal shared in two VFAT  Two thresholds

  11. VFAT digital emulator mezzanine CFEC with mezzanine Top Bottom

  12. VFAT analog emulator mezzanine (1) • We have had some problem with the first pcb design: • Blind hole - Ratio diameter/#layers 1/12, not possible to produce • New PCB Design completed. • Ready to produce the prototype next week. • Components procurement completed. • Pcb production need 1 weeks • Components loading 1 week • Ready to mount on the CSC-5P, middle of October

  13. VFAT analog emulator mezzanine (2)

  14. Mezzanines firmware • VFAT verilog code have been synthesized, routed and placed in the FPGA designed for the mezzanines (Xilinx Spartan 3.) • Need to link the physical pin out of the device with the code. • Need to write the USB driver: • Probably we can adopt the driver written for the FED mezzanine? • We can “play” with the firmware, soon. • Need to get the new VFAT datasheet, in particular I2C registers mapping.

  15. T1 Detector cable routing (1)

  16. T1 Detector cable routing (2)

  17. T1 Detector cable routing (1)

  18. A1733B 28 Channels 3 kV/3 mA or 4 kV/2 mA H.V. architecture DCS SCADA OPC Server Patch -Panel 3 x R.M. 2 2 Patch -Panel Patch -Panel R.M. R.M. 15 SHV 15 SHV 15 SHV 15 SHV R.M. R.M. Patch -Panel Patch -Panel R.M.= 52 Radiall Multipin • GROUNDING & SHIELDING ??

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