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Preshower Collaboration Meeting

Preshower Collaboration Meeting. Status of Work PSD Production and Database Detector Dependent Unit and Related Software Development. PSD Production: Present status in India. Mask for modified geometry of 63mmx63mm has been designed and fabricated

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Preshower Collaboration Meeting

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  1. Preshower Collaboration Meeting Status of Work • PSD Production and Database • Detector Dependent Unit and Related Software Development M.D. Ghodgaonkar, BARC, Mumbai

  2. PSD Production: Present status in India • Mask for modified geometry of 63mmx63mm has been designed and fabricated • The testing facility for carrying out detector qualification tests has been setup at BEL, Banglore • Three test runs have been carried out at BEL, Banglore ( about 60 wafers were processed) • Work related to CRISTAL data base installation has been partly completed M.D. Ghodgaonkar, BARC, Mumbai

  3. PSD Production at BEL, Banglore • Three test runs have been completed at BEL • The yield of the process is improved from about 20% in the first run to to about 50% in the third run • At present another batch of 100 wafers is being processed at BEL M.D. Ghodgaonkar, BARC, Mumbai

  4. PSD Testing Facility at BEL • Two setups for static measurements (IV and CV) have been installed • These setups include automated IV and CV measurement system developed at BARC • Another set of IV and CV setups is built using Keithley 237, 2400 and 590 • Jigs provided by CERN are being used for geometrical measurements ( length, width and thickness). Standards have been made in order to calibrate these jigs. M.D. Ghodgaonkar, BARC, Mumbai

  5. IV Measurement System I-V MEASUREMENT SYSTEM Detector with Probe Card Current to Voltage Conversion H.V. Source Controlled By PC PC with A/D and D/A Cards CV MEASUREMENT SYSTEM CV Measurement system Detector with Probe Card Capacitance to Voltage Conversion H.V. Source Controlled By PC PC with A/D and D/A Card M.D. Ghodgaonkar, BARC, Mumbai

  6. CV measurement system developed by BARC M.D. Ghodgaonkar, BARC, Mumbai

  7. IV measurement system developed by BARC M.D. Ghodgaonkar, BARC, Mumbai

  8. IV/CV measurement system built using Keithley instruments M.D. Ghodgaonkar, BARC, Mumbai

  9. CRISTAL Data Base: Present Status • Email Connectivity of BEL with BARC Regional Centre- Established • Internet Connectivity of BARC Regional Centre- ISDN Dialup connection with static IP has been established and Email/Telnet connectivity with CERN has been tested. • CRISTAL-1 ver 1.2 has been installed but there are problems related to connectivity to CERN • It has been suggested to use CRISTAL-2 software in place of CRISTAL-1 . CRISTAL-2 software will be available in coming spring? • Production data can remain with BARC in ASCII form, and can directly be entered then in new database only? M.D. Ghodgaonkar, BARC, Mumbai

  10. Data Base: Implementation at BEL and BARC Keithley I-V/C-V SYSTEM LOCAL CENTER BARC SERVER COMPUTER AT BEL BARC I-V SYSTEM TO CERN Email BARC C-V SYSTEM M.D. Ghodgaonkar, BARC, Mumbai

  11. Performance of detectors fabricated in recent test-runs • Leakage currents have been measured up to 300V • Capacitance vs Voltage has been measured up to 200 V • The full depletion voltage, total leakage current at full depletion, at 300V and breakdown voltage have been obtained from the LabView software provided by CERN M.D. Ghodgaonkar, BARC, Mumbai

  12. Typical IV and CV characteristics of a good detector M.D. Ghodgaonkar, BARC, Mumbai

  13. Summary of the results of the second test-run M.D. Ghodgaonkar, BARC, Mumbai

  14. Summary of the results of the third test-run M.D. Ghodgaonkar, BARC, Mumbai

  15. Geometrical measurements of detectors after scribing M.D. Ghodgaonkar, BARC, Mumbai

  16. Production schedule • The yield has been improved in the recent test runs to about 50% and a batch of 100 wafers is being processed • The production would be targeted to process about 100-125 wafers per month ( about 50 detectors would be produced in a month) • Could we go ahead for production or the production schedule should be compatible with the micromodule production? M.D. Ghodgaonkar, BARC, Mumbai

  17. I/P from MB (LVDS) O/P from DDU LVDS Receivers S-link-64 LSC DDU-FPGA VME-FPGA SDDU on VME Board M.D. Ghodgaonkar, BARC, Mumbai

  18. I/P from MB Data(16) LVDS I/F I/P FIFO Processing? Clk FifoFull VME I/F AND CNTRL UNIT DDU FPGA E. Data FIFO VME64 O/P FIFO VME-FPGA FEDO/P S-link-64 (LSC) SDDU-Block Diagram M.D. Ghodgaonkar, BARC, Mumbai

  19. . . . . . . . . . . . . . . . . . . . . . . . . The Test Setup for DDU Development Data I/P from Motherboard/Test jig S-link-64 PC (with S-link-64 read-out PCI card) VMEcrate VMIC 7697 VMEbus CPU SDDU Controller Bus Monitor M.D. Ghodgaonkar, BARC, Mumbai

  20. VME-FPGA Functionality • Flex10K50EQC240-2 chip is used. • Contains 3 data buffers (FIFOs), 512x16 each. • Input data clock rate at up to 40 MHz. • Experimental data or online data from MB can be selectively supplied to DDU-FPGA. • The processed data from DDU-FPGA is made available to VMEbus system through output buffer. • VMEbus Interface • Re-organization of K data into common CMS data format can be tested, or something else(?) M.D. Ghodgaonkar, BARC, Mumbai

  21. VMEbus Interface • Meets VME64 Specifications (ANSI/VITA 1-1994) • Data transfer bus: D32/D16: A32/A24/A16 Slave • Address modifier codes: 09H, 0DH, 39H, 3DH, 29H, 2DH • Memory map: Extended,standard or short address space occupying 1024 bytes, base address: jumper configurable or fixed within FPGA. • VME bus access time: 100 ns typical (all registers) • Interrupts: Jumper selectable (1..7) interrupt level and enable under software control. D32, RORA. M.D. Ghodgaonkar, BARC, Mumbai

  22. DDU-FPGA Functionality • Suitable FPGA to be finalized. • Data reduction algorithm to be implemented and tested. • To accommodate LUTs and control information initialized by the VME system. • The processed output to be sent to S-link-64 in common CMS data format or to VMEbus system. • The data samples at various stages of processing to be made available to VMEbus system. (necessary during algorithm development) M.D. Ghodgaonkar, BARC, Mumbai

  23. Status of the SDDU • PCB under fabrication. • VHDL design code under development along with block-by-block simulation . • Simple test jig under fabrication for functional testing of the SDDU board in absence of the MB. • Target date: February, 2003. M.D. Ghodgaonkar, BARC, Mumbai

  24. Some points related to DDU Development • Devices: Apex II and Virtex FPGAs and GBPS transceivers ? • Optical transceivers, TTCrx and associated test jigs • HRK kit (Hardware Readout Kit)? • 9U VME64: VME64x, Speed? • DDU algorithms and FPGA Implementation? • Any other ? M.D. Ghodgaonkar, BARC, Mumbai

  25. XDAQ RELATED DEVELOPEMENT • AIDA3 c++ implementation & XML transformation & visualization (for JAVA) completed. Code to be sent to CERN (Johannes Gutleber) • Software Development for Preshower DAQ using XDAQ and Simulators for hardware? M.D. Ghodgaonkar, BARC, Mumbai

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