Vending Machine Memory Design Using Simple Processor Concepts in VHDL
This project implements a basic vending machine memory system using a simple processor design approach in VHDL. The focus is on developing memory components like RAM and registers to handle data efficiently. The RAM is characterized by its ability to read and write bit data, while the register maintains state using load and reset functionalities. This project serves as an educational resource for understanding digital design, memory architecture, and control mechanisms in VHDL, supported by a clear structure of components and processes involved.
Vending Machine Memory Design Using Simple Processor Concepts in VHDL
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Presentation Transcript
Main Project : Simple ProcessorMini-Project : Vending MachineMemory By Oluwayomi B. Adamo
Design Specification • Memory • Register • Programming Counter • Instruction Register • ALU • Control Unit • Input • Output
Memory(VHDL) ENTITY ram IS GENERIC ( bits: INTEGER := 8; -- # of bits per word words: INTEGER := 16); -- # of words in the -- memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO words-1; data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0); data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)); END ram; --------------------------------------------------- ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR (bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS (clk, wr_ena) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in; END IF;
Memory contd. END IF; END PROCESS; data_out <= memory(addr); END ram;
Register(VHDL) • entity reg is port( clk, ld, rst : in std_logic; Data: in std_logic_vector( 2 downto 0); Q: out std_logic_vector( 2 downto 0)); • end reg; • architecture behv of reg is • signal Q_tmp: std_logic_vector( 2 downto 0); • begin • process(clk, ld, rst, data) • begin • if (rst = '0' )then • Q_tmp <= (Q_tmp'range => '0'); • elsif (clk='1' and clk'event) then • if (ld = '1' )then • Q_tmp <= Data; • end if; • end if; • end process; • Q <= Q_tmp; • end behv;
