'Daughter card' diaporamas de présentation

Code Composer Studio and the DSKs DSK6711, DSK6713 and DSK6416

Code Composer Studio and the DSKs DSK6711, DSK6713 and DSK6416. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004. Learning Objectives. Introduction to C ode C omposer S tudio - CCS Installation and Setup of CCS. Introduction to the DSK-TI.

917 views • 49 slides

System Level Signal Integrity

System Level Signal Integrity. Jeff Cain HW Engineering Manager. Outline. SI Engineering Gigabit/second technology Digital communication Future. SI Engineering. Signal Integrity Engineer This phrase/title did not exist 7 years ago Technology was leading to a divide

358 views • 31 slides

NAS vs. SAN Presentation

Compare NAS with SAN. Introduction to Wolfman. What is Scyld from Penguin. NAS vs. SAN Presentation. Traditional Mode ? DAS. Direct. Attached. Storage. What is NAS?. High performance for data access. Ease of installation and management. Base on Ethernet Infrastructure. What is SAN?.

499 views • 21 slides

XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing

XFEL 2D Pixel Clock and Control System. XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing. OUTLINE. June meeting at DESY C&C Hardware structure C&C Firmware structure Current Status Outstanding Issues Future plans. June Meeting at DESY.

317 views • 19 slides

Virtex-II Pro PowerPC SEE Characterization Test Methods and Results

Virtex-II Pro PowerPC SEE Characterization Test Methods and Results. David Petrick 1 , Wesley Powell 1 , Ken LaBel 1 , James Howard 2 1 NASA Goddard Space Flight Center, Greenbelt, MD 20771 2 Jackson & Tull, Seabrook, MD 20706. Abstract.

267 views • 16 slides

STATIC DIGITAL BOARD MAY 12, 2010

STATIC DIGITAL BOARD MAY 12, 2010. Rick Sterling. Digital Board Status. Engr Model working with PFDP Simulator, TDC, Sweep/Deflector Minor changes to board circuits and parts for next version Major change will be implementation of daughter card to carry the FPGA. Interconnect Overview.

243 views • 15 slides

Data Collection Module (DCM) (review, fabrication plan & chain test)

Data Collection Module (DCM) (review, fabrication plan & chain test). DCM team Cheng-Yi Chi ( DCM, TOF FEE, BB FEE) Jamie Nagle (DCM) Bill Sippach (DCM, TOF FEE, BB FEE) Herb Cunitz (DCM, TOF FEE, BB FEE) Li Zhang (DCM, TOF FEE, BB FEE). DCM Functions. Zero-suppress FEM data

116 views • 11 slides

Belle II numbering

Belle II numbering. y. y. x. x. z. z. Electronics mapping ( rawdata ). col 2. col 1. col 0. col 3. r ow: carrier level, 0-3. c olumn: daughter card slot, 0-3. c hannel: channel on ASIC, 0-7. r ow 3. r ow 2. r ow 1. 6 4 2 0. r ow 0. 7 5 3 1. 6 4 2 0. 7 5 3 1. channel.

186 views • 10 slides

PHENIX upgrade DAQ Status/ HBD FEM experience (so far)

PHENIX upgrade DAQ Status/ HBD FEM experience (so far). The thoughts on the PHENIX DAQ upgrade Slow download HBD test experience so far GTM FEM readout (DCM). Ethernet in PHENIX Upgrades.

195 views • 7 slides

HBD upgrade status.

76 views • 7 slides

Yuri Ermoline Level-1 Calorimeter Trigger General Meeting, CERN December 15, 2011

VME test card for VME/ACE/TTC interface for CMX. Yuri Ermoline Level-1 Calorimeter Trigger General Meeting, CERN December 15, 2011. Initial idea. VME CPLD. VME/TTC/ACE parts of CMM 2 CPLDs + 1 FPGA Redesign HW with new components Parts obsoleteness Merge VHDL a single design

120 views • 4 slides

Yuri Ermoline Level-1 Calorimeter Trigger General Meeting, CERN December 15, 2011

VME test card for VME/ACE/TTC interface for CMX. Yuri Ermoline Level-1 Calorimeter Trigger General Meeting, CERN December 15, 2011. Initial idea. VME CPLD. VME/TTC/ACE parts of CMM 2 CPLDs + 1 FPGA Redesign HW with new components Parts obsoleteness Merge VHDL a single design

46 views • 4 slides