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Simulation of Finite Geometry LDPC code on the Packet Erasure channel

Simulation of Finite Geometry LDPC code on the Packet Erasure channel

Simulation of Finite Geometry LDPC code on the Packet Erasure channel. Wu Yuchun July 2007. Huawei Hisi Company Ltd. Contents. Abstract. A simple example of encoding and decoding of FG_LDPC code Performance Metrics and FEC parameters Simulation Result of Inefficient Ratio

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372 views • 24 slides
Non-Binary Joint Network Channel Coding for Reliable Communication in Large Wireless Networks

Non-Binary Joint Network Channel Coding for Reliable Communication in Large Wireless Networks

Non-Binary Joint Network Channel Coding for Reliable Communication in Large Wireless Networks. Zheng Guo , Jie Huang, Bing Wang, Jun-Hong Cui and Shengli Zhou. Outline. Motivation Related Work System Description Benefits of NB-JNCC Performance Study Conclusions & Discussions. Motivation.

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307 views • 19 slides
Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title : LDPC Code Performance and Complexity Comparing with Convolutional and RS Code Date Submitted: [01 Sept 2009] Source: [Qin Wang ] Company [ University of Science & Technology Beijing ]

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183 views • 12 slides
Low Complexity, High throughput wireless architecture

Low Complexity, High throughput wireless architecture

Digital Up Converter. Digital to Analog Converter. Transmitter Front-End. Symbols. IFFT, Add CP. Computer. Packet Detection Timing Recovery, Remove CP, FFT. Digital Down Converter. Analog to Digital Converter. Receiver Front-End. Symbols. Analog Impairment. FPGA.

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128 views • 1 slides
Low Complexity, High throughput wireless architecture

Low Complexity, High throughput wireless architecture

Digital Up Converter. Digital to Analog Converter. Transmitter Front-End. Symbols. IFFT, Add CP. Computer. Packet Detection Timing Recovery, Remove CP, FFT. Digital Down Converter. Analog to Digital Converter. Receiver Front-End. Symbols. Analog Impairment. FPGA.

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97 views • 1 slides

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