1 / 19

Introduction to Micro Controllers & Embedded System Design

Introduction to Micro Controllers & Embedded System Design. Department of Electrical & Computer Engineering Missouri University of Science & Technology hurson@mst.edu.

shayna
Télécharger la présentation

Introduction to Micro Controllers & Embedded System Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction to Micro Controllers&Embedded System Design Department of Electrical & Computer Engineering Missouri University of Science & Technology hurson@mst.edu A.R. Hurson

  2. Stored Program Machine: A computer with a storage component that may contain both data to be manipulated and instructions to manipulate the data is called a stored program machine. This simply implies that the user is able to change the sequence of operations on the data. • Program: The sequence of operations performed on the data is called a program. More formally, it is a finite set of instructions that specify the operands, operations, and the sequence by which processing has to occur. A.R. Hurson

  3. Instruction: An instruction is a group of bits that tells the computer to perform a specific operation. It is composed of two parts: • Operation part • Operand part A.R. Hurson

  4. Operation part(operation code) is a group of bits that defines the action to be performed. • For each machine the set of operations is limited and defined. • In general, a machine with n bits as op.code is capable of supporting 2n distinct operations each having a distinct encoding as op.code. A.R. Hurson

  5. Operand part defines the element (s) needed for operation. • Within the scope of a program, besides the op.code, one needs four pieces of information (note majority of operations are binary operations): • 2 operands as sources • 1 operand as a destination • 1 operand to specify the location of the next instruction that should be fetched. A.R. Hurson

  6. Depending on how many of these pieces of information are explicitly defined, instructions are grouped into 5 classes: 4, 3, 2, 1, and 0-address instructions. A.R. Hurson

  7. Register addressing • In 8051 programmer has access to eight “working registers” numbered R0 to R7. • Three least significant bits of op.code are used to specify a register. • The 8051 assembly language indicates register addressing with the symbol Rn (0  n  7). A.R. Hurson

  8. Register addressing • Example ADD A, R7 1 1 1 0 1 1 1 1 Op.code Op.code register Register Instruction format A.R. Hurson

  9. Implied • Some instructions are referring to specific register such as A (accumulator), DPTR (data pointer), PC (program counter), and B register so address bits are not needed. In another words, op.code indicates the register involved in the operation. • Example INC DPTR MUL AB A.R. Hurson

  10. Direct addressing • Direct addressing allows access to any on-chip variable or hardware register. An additional byte is appended to the op.code specifying the location to be used. • Example MOV P1, A Direct addressing Op.code Instruction format A.R. Hurson

  11. Indirect addressing • In 8051, R0 and R1 may operate as a “pointer” register. In this case, the low order bit of op.code indicates which register. • In 8051assembly language, indirect addressing is identified as “@” preceding either R0 or R1. A.R. Hurson

  12. Indirect addressing • Example: Assume R1 contains 40H and internal memory address 40H contains 55H, then the instruction MOV A, @R1 moves 55H into the accumulator Op.code Instruction format R0 or R1 A.R. Hurson

  13. Immediate addressing • In assembly language of 8051, immediate addressing is identified by “#” symbol. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constant, symbols, and operators. Assembler calculates the expression and substitutes the result into the instruction. Immediate data Op.code Instruction format A.R. Hurson

  14. Immediate addressing • Example: MOV A, #12 • Note: There is just one exception when initializing the data pointer, we need a 16-bit constant, therefore MOV DPTR, #8000H is a 3-byte instruction with a 16-bit constant 8000H. A.R. Hurson

  15. Relative addressing • This addressing mode is used with certain jump instructions. A relative address is an 8-bit signed value which is added to the contents of the program counter to form address of the next instruction to be fetched and executed. • Naturally, the range for jump is -128 to +127 locations. Relative offset Op.code Instruction format A.R. Hurson

  16. Relative addressing • Example: Assume label THREE represents an instruction at location 1040H and instruction SJMP THREE is in memory location 1000H and 1001H, then the assembler assigns a relative offset of 3EH as byte-two of the instruction since 1002H + 3EH = 1040H A.R. Hurson

  17. Absolute addressing • Absolute addressing is just used with ACALL and AJMP instructions. These 2-byte instructions allow branching within the current 2K page of code memory by providing the 11 least significant bits of destination address in op.code (i.e., A10-A8 and byte 2 of instruction A7-A0). A7-A0 Op.code A10-A8 Instruction format A.R. Hurson

  18. Absolute addressing • The upper five bits of the destination address are the current value of the upper five bits of program counter. Therefore, the next instruction after the branch and the destination instruction must be within the same 2K page. A.R. Hurson

  19. Index addressing • Index addressing uses a base register (either the program counter or the data pointer) and an offset (the accumulator) in forming the effective address for JMP or MOVC instructions. • Example: MOVC A, @A+PC PC or DPTR + ACC = effective address Offset Base register A.R. Hurson

More Related