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SoCET: Cortex-M0™ Debugging Unit for SoC Designs - ARM University Integration Solution

This SoCET project developed by a team led by Dr. Matthew Swabey offers a comprehensive debugging unit designed with Verilog for synthesis and System Verilog for testing. The debugging unit features a Hierarchical Finite State Machine structure, making it extensible and ensuring code reuse while supporting state/trigger-based and entry/exit-based actions. By incorporating OVL Assertions, this debugger enhances error observability by checking for correct input command and appropriate state transitions. The project’s primary aim is to provide universities with a Cortex-M0™ processor integration solution into their System on Chip designs that communicate over a standard serial port with minimal hardware requirements.

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SoCET: Cortex-M0™ Debugging Unit for SoC Designs - ARM University Integration Solution

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  1. SoCET – System On Chip Extension Technologies Open Cortex-M0™ DesignStart Debug Unit • ARM developed the Cortex-M0™ Core processor • Available to Universities for integration into SoC designs • University version is limited due to removal of the debugging unit. • Features: • Communicates over a standard serial port • Widely available • Uses only two pins on the chip • Standard Debugger Features • Read/Write from any memory location • Read processor state • Implementation: • Debugging Unit Designed with Verilog for Synthesis • Test Benches Designed with System Verilog for Testing • Debugging Unit has a Hierarchical Finite State Machine structure • Extensible • Simplifies the state space • Guarantees code reuse • Supports state/trigger based and entry/exit based actions • Usage of OVL Assertions in the Debugger • Increases observabililty of error in the design • Assertions check for • Correct input command • Appropriate transition of sub-states • Ensures sub-state counters never reach zero Team Members: Andrew Brito, Richard Park, Chuan Yean Tan, XinTzeTeeand Todd Wild Lead by:Dr. Matthew Swabey

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