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Jianhui Gu The Ohio State University

A Digital CFEB for CSC upgrade. Jianhui Gu The Ohio State University. Current CFEB design. Production version: Nov. 2001 Functional diagram:. OUT1. 12+1bit. 40MHz. 280 Mbps. DMB. SCH1-16. CH1-16 Layer 1. 6.7 MHz. ADC. SCA. 12+1bit. 21:3 CL. TCH1-16. 6: 1mux. BUCKEYE.

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Jianhui Gu The Ohio State University

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  1. A Digital CFEB for CSC upgrade Jianhui Gu The Ohio State University

  2. Current CFEB design • Production version: Nov. 2001 • Functional diagram: OUT1 12+1bit 40MHz 280 Mbps DMB SCH1-16 CH1-16 Layer 1 6.7 MHz ADC SCA 12+1bit 21:3 CL TCH1-16 6:1mux BUCKEYE HS_CH1-8 TMB 24 LVDS converter COMPARATOR HS_CH1-8 2:1mux CH1-16 Layer 6 • Bottleneck: • * SCA single output channel to ADC • 20ms per event for eight time sample (400ns) readout, • Constraint on the LCT/L1A latencies (<3.2ms) & SCA depth • * Channel link • SkewClear Cable, limited to ~17 meter (ME1/1 on border)

  3. Proposed Digital CFEB • * Technology Development: Serial Links, FPGA: • Multi-channel ADC in a small package (Analog Devices: AD9222) • Multi-gigabit Transceiver, high speed serial link on FPGA • Large memory inside FPGA * Functional diagram: 20MHz 8-ch 12-bit ADC 8 Memories @240Mbps / 2 as DDR DMB LCT MGT 8 SCH1-16 20MHz 8-ch 12-bit ADC CH1-16 Layer 1 TCH1-16 BUCKEYE L1A HS_CH1-8 TMB 24 LVDS converter COMPARATOR HS_CH1-8 2:1mux CH1-16 Layer 6 MGT FPGA Three layers of memories: Before LCT, between LCT and L1A, after L1A No dead time for LCT&L1A matching (readout) rate of ~50KHz

  4. Digital CFEB • To current DMB/TMB: • OK: FPGA firmware control, possibility of slower data rate for longer cables for DAQ. • To ‘new’ DMB/TMB with fiber link: • Better: FPGA firmware control, Fit more CFEBs per DMB/TMB 7.5”

  5. Digital CFEB • Power Consumption comparison: Current CFEB: ~ 10 W Digital CFEB: ~ 15-20 W • Cost: Digital CFEB ~$1400, (compatible with current CFEB)

  6. Digital CFEB • Option 1: Build Digital CFEBs for ME1/1 (move Current CFEBs to ME4/2) • Total Digital CFEB: 72*5*(1+15%) = 414 • Option 2: Build Digital CFEBs for full readout of ME1/1(A) • Total CFEB: 72*7*(1+15%) = 580 • Question 1: Plan for new LVDB? • Lower voltage, higher current (esp. +1.8V) • Question 2: New DMB/TMB schedule? • Digital CFEB IO interface • Question 3: Size of the Digital CFEB? • The width stays the same (determined by chamber input • cables), the length can be reduced. Most likely keeping the current size

  7. BACKUP slide Cost estimate (from Feb. 2008)

  8. Digital CFEB • Cost Estimate: • ~$1400 per new CFEB • ADC: Analog Device: AD9252 ($50 more)/AD9222 ($100 less) • FPGA: Xilinx, Virtex-4? ~350 IO, 1 Mb RAM, 2 MGT

  9. Digital CFEB • Total Cost: • Option 1: ME4/2 addition (ME1/1 swapping) • Total CFEB: 72*5*(1+15%) = 414 • Total cost: $1400*414 = $580K + spare parts + R/D + labor • Option 2: ME4/2 addition and ME1/1/A full readout • Total CFEB: 72*7*(1+15%) = 580 • Total cost: $1400*580 = $812K + spare parts + R/D + labor • * In both cases, The SLHC issue is dealt with assuming that the ME1/1 has the highest data rate (much higher than other chambers) • * The new DMB design cost (if there will be a new design, the ME1/1A full readout requires new DMB) can be balanced by replacing the costly skew-clear cables

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