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Passive Distortion Compensation for Package Level Interconnect Dongsheng Ma & Janet Wang Univ. of Arizona Chung-Kuan Cheng UC San Diego
Outline • Motivation • Review of High-Speed Serial Links • Passive Distortion Compensation • Theory • Implementation • Simulation Results • Power Management and System Integration • Research Direction
Normalized unit to 90nm node Technology (nm) 1. Motivation: ITRS Bandwidth Projection Courtesy of Hamid Hatamkhani et al., DAC ‘06 • Abundant on-chip bandwidth • Off-chip bandwidth is the bottleneck • Many chip are I/O limited
3. Passive Distortion Compensation Distortionless Transmission Line Typical RLC Transmission Line Intentionally make leakage conductance satisfy R/G=L/C Frequency response becomes flat from DC mode to Giga Hz Frequency dependent phase velocity (speed) and attenuation
3.1 Theory: Telegrapher’s Equations • Telegrapher’s equations • Wave Propagation • Propagation Constant • Characteristic Impedance • and correspond to attenuation and phase velocity. Both are frequency dependent in general.
3.1 Theory: Distortionless Lines • Distortionless transmission line If Both attenuation and phase velocity become frequency independent
3.1 Theory: Differential Case Common Mode – Current flowing in the same direction Differential Mode – Current flowing in the opposite direction Shunt between each line to ground Shunt between the two lines
3.2 Implementation • Evenly add shunt resistors between the signal line and the ground • Non-ideality
3.2 Implementation: MCM trace MCM trace vs. On-chip interconnect On-chip MCM ~10 cm ~ 10 mm Length Series Resistance 1 Ω/mm 1 Ω/μm Frequency dependency of line parameters Large Small Operation region RLC RC
3.2 Implementation: A MCM Stripline Case • Control the signal line thickness to minimize skin effect (cost vs. distortion) • Assume LCP dielectric Geometry based on IBM high-end AS/400 system
3.3 Simulation: Methodology • Transient simulation in Hspice • Each transmission line segment is modeled by W-element using frequency-dependent tabular model • Discrete resistors • Used CZ2D tool from IBM for RLGC extraction • Part of IBM EIP (Electrical Interconnect & Packaging) suite. • Fast and accurate • Ensures causality of transient simulation
3.3 Simulation: RLGC vs. Frequency • Match at DC • Boost up low frequency traveling speed • Balance low frequency attenuation and high frequency attenuation R L C G Z0 = 78 Ω, delay = 57.78 ps/cm R1MHz=11.07 Ω/cm, L1MHz=5.52e-3 μH/cm, C1MHz =0.74 pF/cm Rshunt =L1MHz/R1MHzC1MHz = 669.5 Ω/cm
3.3 Simulation: Shunt Resistor Spacing • Number of shunt resistors = N • Resistors are implemented with embedded carbon paste film • Spacing depends on the target data rate
3.3 Attenuation • W8μm/t2μm/b20μm
3.3 Phase Velocity • W8μm/t2μm/b20μm
3.3 Simulation: Pulse Response DC saturation voltage determined by the resistor ladder less severe ISI effect
3.3 Jitter and Eye opening for 2um case • W8μm/t2μm/b20μm • Each shunt resistor is 669.5 ohm • Z0=78 ohm • For 10cm line, Rdc = 66.9 ohm; for 20 cm line, Rdc=33.5 ohm
3.3 Jitter and Eye opening for 4.5um case • W8μm/t4.5μm/b20μm • Each shunt resistor is 1232 ohm • Z0=71.1 ohm • For 10cm line, Rdc = 123.2 ohm; for 20 cm line, Rdc=61.6 ohm
3.3 Simulation: Eye Diagrams • W8μm/t2μm/b20μm/L10cm • 1000 bit PRBS at 10Gbps • W-element + tabular RLGC model in HSpice Without shunt resistors With 10 shunts (each = 669.5) Reduced amplitude Clear eye opening Jitter = 5.57 ps Eye opening = 0.426 V Jitter = 22.5 ps Eye opening = 0.51 V
3.3 Best Eye Diagram for 2um thick case • W8μm/t2μm/b20μm/L10cm, 10 distributed resistors Eye opening Jitter Best case when each shunt is 500 ohm Jitter = 4.63 ps Eye opening = 0.35645 V Jitter & eye opening v.s. shunt value
Best eye diagram when only terminator is used, 2um thick case • W8μm/t2μm/b20μm/L10cm, terminator only Eye opening Jitter Jitter & eye opening v.s. R_term Best case when terminator 90 ohm Jitter = 4.97 ps Eye opening = 0.40647 V
W8μm/t2μm/b20μm/L20cm, 20 distributed resistors Eye opening Jitter Best case when each shunt is 600 ohm Jitter = 9.816 ps Eye opening = 0.08379 V Jitter & eye opening v.s. shunt value
W8μm/t2μm/b20μm/L20cm, terminator only Eye opening Jitter Jitter & eye opening v.s. R_term Best case when terminator 40 ohm Jitter = 11.95 ps Eye opening = 0.10111 V
3.3 Eye Diagram for 4.5um thick case when matched at DC • W8μm/t4.5μm/b20μm/L10cm Open ended 10 shunts matched at DC Jitter = 22.8 ps eye opening = 0.525 V Sleepy Eye
3.3 Best Eye Diagram for the 4.5um thick case • W8μm/t4.5μm/b20μm/L10cm, 10 distributed resistors Eye opening Jitter Best case when each shunt is 500 ohm Jitter = 11.97 ps Eye opening = 0.44036 V Jitter & eye opening v.s. shunt value
W8μm/t4.5μm/b20μm/L10cm, terminator only Eye opening Jitter Best case when the terminator is 80 ohm Jitter = 7.18 ps Eye opening = 0.51672 V Jitter & eye opening v.s. R_term
W8μm/t4.5μm/b20μm/L20cm, 20 distributed resistors Eye opening Jitter Best case when each shunt is 800 ohm Jitter = 21.762 ps Eye opening = 0.18288 V Jitter & eye opening v.s. shunt value
W8μm/t4.5μm/b20μm/L20cm, terminator only Eye opening Jitter Best case when the terminator is 110 ohm Jitter = 37.595 ps Eye opening = 0.24859 V Jitter & eye opening v.s. R_term
3.3 Eye Diagram for the MCM trace • W8μm/t4.5μm/b20μm/L20cm Terminated with Z0 20 shunts matched at DC Jitter = 38.834 ps Eye opening = 0.21418 Jitter = 23.24 ps eye opening = 0.238 V
4. Adaptive Power Management (APM) • The distortionless signaling simplifies the interface circuitry. However, the twice heavier attenuation due to passive compensation calls for adaptive power management; • With adaptive power management, we adaptively regulate the power supply of the transmitter according to attenuation; • The regulated supply voltage guarantees the speed of transmission while keeping the minimal power overhead and well-controlled bit-error rate.
4. System Integration • The reduction of the jitter leaves larger design margin for interface circuit design; • To enable an effective and accurate communication, the operation of transmitter and receiver must be well synchronized. This requires accurate clock positioning and phase locking; • Synergic method will be taken to achieve mutual compensation and joint leverage on signal accuracy, attenuation and system power.
5. Research Direction • Develop analysis models for the technology • Eye diagram analysis via step responses • Power consumption • Optimize technologies • Chip carrier and board technologies • Redistribution • Physical dimensions • Shunts, terminators • Prototype fabrication & measurement • More applications: clock trees, buses • Incorporate transmitter/receiver design
Remark • Distortion Compensation: • Source termination: Impedance • Receiver termination: Voltage Clamp, Matched Z, Optimized Z. • Distributed shunts • Combination of above techniques • Packaging • Current Products: Improve signal quality based on current fabrication technologies. • Future Products: Devise the optimal combination.
The End Thank you!