shiro
Uploaded by
18 SLIDES
345 VUES
180LIKES

Smart Responder: Timed Competitor Response System with Input Verification

DESCRIPTION

The Smart Responder project developed by Abrahem Al-afandi and Ann Goodyear aims to create an interactive system that tests which competitor presses a responder first. It features two timing configurations (15s and 60s) using frequency dividers, alongside a mechanism for recording total points accrued by each competitor. The system includes rigorous testing phases with several test benches, ensuring input answers are compared against a master solution for accuracy. The design integrates RTL synthesis and layout verification to optimize connectivity and geometry.

1 / 18

Télécharger la présentation

Smart Responder: Timed Competitor Response System with Input Verification

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

Playing audio...

  1. EE 330 Final project Abrahem Al-afandi Ann Goodyear

  2. Smart Responder • Test who is the first one to press the responder. • Designing timers: 15s and 60s with Freq. divider. • Recording the total points each competitor obtained. • Comparing input answers to the master solution.

  3. Code

  4. Code (Cont.)

  5. Test Bench 1

  6. Test Bench 1 SImulation

  7. Test Bench 2

  8. Test Bench 2 Simulation

  9. Test Bench 3

  10. Test Bench 3 Simulation

  11. Test Bench 4

  12. Test Bench 4 Simulation

  13. RTL Synthesis

  14. Power & Placement

  15. Route & Filter Cell

  16. Connectivity & Geometry

  17. Virtuoso Layout

  18. DRC Verification

More Related