1. CMOS Monolithic Active Pixel Sensors R. Turchetta CMOS Sensor Design Group Rutherford Appleton Laboratory, Oxfordshire, UK

2. Outline • CMOS Image Sensors @ RAL • The INMAPS process and its silicon proof • Conclusions

3. CMOS image sensor activity started in 1998 (aka Monolithic Active Pixel Sensor; MAPS) 1st tape-out in 2000: test structures for the Star-Tracker in 0.5 and 0.7 mm 1st full-scale sensor submitted in May 2001: the Star-Tracker in 0.5 mm Use of technologies down to 0.18 mm Use of CIS (CMOS Image Sensors) technologies Patented, silicon-proofed INMAPS technologyfor high-end sensors Pixel size from 2 mm upwards Large pixels IPs 4T pixel Ips Low noise pixel IPs Wafer-scale (200mm) sensor capability Over 40 years of cumulateddesign experience Overall view

4. The Large Area Sensor (LAS) Sensors of different sizes on the same 200mm wafer 0.35 mm CMOS Basic unit 270x270 pixels X5  1350x1350 X2  540x540 X1  270x270 Wafer-scale possible

5. Region of Reset readout Image of a laser point ROR readout Tint0 = 80, Tint1 = 30, Tint2 = 1 No ROR >140dB

6. How much CMOS in a CMOS sensor? NMOS Diode NMOS PMOS N+ N+ N+ N+ P+ P+ N-Well P-Well P-Well N-Well P-substrate (~100s mm thick) 100 % efficiency  only NMOS in pixel  no complicated electronics Complicated electronics  NMOS and PMOS,i.e. CMOS  low efficiency

7. The INMAPS process NMOS Diode NMOS PMOS N+ N+ N+ N+ P+ P+ N-Well P-Well P-Well N-Well Deep P-Well P-substrate (~100s mm thick) Standard CMOS with additional deep P-well implant. Quadruple well technology. 100% efficiency and CMOS electronics in the pixel. Optimise charge collection and readout electronics separately! • Proved on 0.18 mm • 7 metal layers • Analog & Digital @ 1.8v & 3.3v • Choice of epi layers (5 and 12 mm tested so far)

8. INMAPSProof of principle Diode pad calorimeter MAPS calorimeter PCB ~0.8 mm Silicon sensor 0.3mm Tungsten 1.4 mm Embedded VFE ASIC • Alternative to CALICE Si/W analogue ECAL • No specific detector concept • “Swap-in” solution leaving mechanical design unchanged

9. preShape Gain 94uV/e Noise 23e- Power 8.9uW 150ns “hit” pulse wired to row logic Shaped pulses return to baseline Pixel Architectures • preSample • Gain 440uV/e • Noise 22e- • Power 9.7uW • 150ns “hit” pulse wired to row logic • Per-pixel self-reset logic 9

10. preShape Pixel 4 diodes 160 transistors 27 unit capacitors 1 resistor (4Mohm) Configuration SRAM Mask Comparator trim (4 bits) 2 variants: subtle changes to capacitors Pixel Layouts Deep p-well Diodes Circuit N-Wells • preSample Pixel • 4 diodes • 189 transistors • 34 unit capacitors • Configuration SRAM • Mask • Comparator trim (4 bits) • 2 variants: subtle changes to capacitors 10

11. 8.2 million transistors 28224 pixels; 50 microns; 4 variants Sensitive area 79.4mm2 of which 11.1% “dead” (logic) Test Chip Architecture • Four columns of logic + SRAM • Logic columns serve 42 pixels • Record hit locations & timestamps • Local SRAM • Data readout • Slow (<5Mhz) • Current sense amplifiers • Column multiplex • 30 bit parallel data output

12. Sensor Testing: Overview • Test pixels • preSample pixel variant • Analog output nodes • Fe55 stimulus • IR laser stimulus • Single pixel in array • Per pixel masks • Fe55 stimulus • Laser Stimulus • Full pixel array • preShape (quad0/1) • Pedestals & trim adjustment • Gain uniformity • Crosstalk • Beam test quad0 quad1 12

13. Charge collection • Amplitude results • With/without deep pwell • Compare • Simulations “GDS” • Measurements “Real” • (pixels with full electronics) Pixel profiles F 13 B

14. 55Fe Source • 55Fe gives 5.9keV photon • Deposits all energy in “point” in silicon; 1640e− • Sometimes will deposit maximum energy in a single diode and no charge will diffuse •  absolute calibration! • Binary readout from pixel array • Need to differentiate distribution to get signal peak in threshold units (TU) • Differential approximation 14

15. Conclusions CMOS Active Pixel Sensors are mature for high-end applications Cost-effective solution for large-scale experiments Low noise (< 10 e- rms) Large area: up to 200mm wafer-scale INMAPS process allows complex in-pixel architectures without degrading the detection performance Evaluating possibility of offering access to the INMAPS process to the community

16. Acknowledgements For the Large Area Sensor (work carried out under the MI-3 Multidimensional Integrated Intelligent Imaging Consortium) A.T. Clark, N. Guerrini, J.P. Crooks, T. Pickering (Rutherford Appleton Laboratory) N. Allinson (University of Sheffield) S.E. Bohndiek (University College London) For the CALICE-MAPS: J.P. Crooks, R. Coath, M. Stanitzki, K.D. Stefanov, M. Tyndel, E.G. Villani (Rutherford Appleton Laboratory) J.A. Ballin, P.D.Dauncey, A.-M. Magnan, M. Noy (Imperial College London) Y. Mikami, N.K. Watson, O. Miller, V. Rajovic, J.A. Wilson (University of Birmingham)