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An Introduction to Digital System Design and PLDs

An Introduction to Digital System Design and PLDs. Sharif University of Technology Department of Computer Engineering. Alireza Ejlali. Advantages of Digital Systems. High noise immunity Adjustable precision Ease of design (automation) and fabrication (low cost) Better Reliability

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An Introduction to Digital System Design and PLDs

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  1. An Introduction to Digital System Design and PLDs Sharif University of Technology Department of Computer Engineering Alireza Ejlali

  2. Advantages of Digital Systems • High noise immunity • Adjustable precision • Ease of design (automation) and fabrication (low cost) • Better Reliability • Less need to calibration and maintenance • Ease of diagnosis and repair • Easy to duplicate circuits • Easily controllable by computer

  3. Abstraction Levels

  4. Y Chart

  5. Y-Chart

  6. Why programmable logic? • TTM (Time-to-market) • EDA/CAD Tools • PLDs • Prototyping • Reconfigurable computing • Custom computing

  7. Advantages of PLDs • Field Programmable • Reduced TTM • Custom computing • Erasable and reprogrammable • Updating a device or correction of errors. • Reuse the device for a different design. • Ideal for course laboratories.

  8. Programmable Logic Technologies • Read Only Memory (ROM) • Programmable Array Logic (PAL) • Programmable Logic Array (PLA) • Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA)

  9. ROM, PAL and PLA Configurations Fixed Programmable Programmable Inputs Outputs AND array Connections OR array (decoder) (a) Programmable read-only memory (PROM) Programmable Programmable Fixed Inputs Outputs Connections AND array OR array (b) Programmable array logic (PAL) device Programmable Programmable Programmable Programmable Outputs Inputs Connections Connections AND array OR array (c) Programmable logic array (PLA) device

  10. X X X D7 D6 X X D5 X D4 D3 A2 A X D2 X X B A1 D1 X A0 D0 C F0 F2 F1 F3 ROM

  11. AND gates inputs 0 1 2 3 4 5 6 7 8 9 Product 1 X term F 2 1 X X 3 I A 5 1 4 X X X F 5 2 X X 6 X X I B 5 2 7 X X F 8 3 X X 9 X I C 5 3 10 X X F 11 4 X X 12 X I 4 0 1 2 3 4 5 6 7 8 9 PAL

  12. A B C A B X 1 X X X B C X X 2 X Fuse intact X Fuse blown A C X 3 X X A B X X 4 X X 0 C C B B A A 1 X F 1 F 2 PLA

  13. FPGA

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