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FE8113 ”High Speed Data Converters”

FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration. Gain errors and calibration - Introduction to gain error calibration and test signal injection in pipelined ADCs. Pipelined ADC. Digital error correction. 1 bit, no error correction:. 1.5 bits, error correction:.

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FE8113 ”High Speed Data Converters”

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  1. FE8113 ”High Speed Data Converters”

  2. Part 2: Digital background calibration

  3. Gain errors and calibration- Introduction to gain error calibration and test signal injection in pipelined ADCs

  4. Pipelined ADC

  5. Digital error correction 1 bit, no error correction: 1.5 bits, error correction: Offset translates directly to distortion at the output Offset within +/-Vref/4 corrected by redundant bits

  6. MDAC gain error φ1: φ2:

  7. MDAC gain error φ2:

  8. Pipeline with gain error

  9. Pipeline with gain error

  10. Calibration of gain error

  11. Calibration of multiple stages

  12. Calibration, alternative implementation (Digital scaling factors between the stages are not shown here)

  13. Test signal injection

  14. Stage transfer function (TF)

  15. Stage TF with Vref/4 test signal

  16. Stage TF, modified test signal, tsmod

  17. MDAC, holding phase, test signal injection

  18. Test signal at ADC output

  19. Measuring error energy Correlate over a blocklength (BL) of millions of samples Error energy at the output, use this to adjust digital coefficient

  20. List of Papers • Test signal injection • E.Siragusa, I.Galton: “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC” • Skip (& fill) • U-K.Moon, B-S.Song: “Background Digital Calibration Techniques for Pipelined ADC’s” • E.B.Blecker et.al: “Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a Simplified Queue” • Slow-but accurate parallel ADC • S.R.Sonkusale et.al: “Background Digital Error Correction Technique for Pipelined Analog-Digital Converters” • X.Wang et.al: ”A 12-bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background Calibration” • J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” • Reference voltage scaling • J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” • S.Sonkusale, J.Van der Spiegel: “Mixed-Signal Calibration of Pipelined Analog-Digital Converters” • Comparator Dithering • A.Gines et.al: “Full Calibration Digital Techniques for Pipeline ADCs” • J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined ADCs” • J.Li et.al: “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy” • Others • A.Abdelatty, K.Nagaraj: “Background Calibration of Operational Amplifier Gain Error in Pipelined A/D Converters” • K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC” • B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification” • Y.Chiu et.al: “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters”

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