Optimality Study of Logic Synthesis for LUT-Based FPGAs

1. Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich VLSI CAD Lab Computer Science Department University of California, Los Angeles Supported by Altera, Xilinx, and Magma under the California MICRO program.

2. Outline • Motivation and background • Current testcases hinted towards algorithms not having much room for improvement. • LEKO • Logic synthesis Examples with Known Optimals • Creation, optimality, and results • LEKU • Logic synthesis Examples with Known Upper bounds • Creation and results • Conclusion UCLA VLSICAD LAB

3. Goals of Paper • Goal was to test the optimality of two design steps for logic synthesis: • Technology Mapping • Logic Optimization combined with Technology Mapping • Definitions • Technology Mapping • Logic Optimization • Logic Synthesis = Logic Optimization + Technology Mapping UCLA VLSICAD LAB

4. Motivation • Logic synthesis is NP-hard in general • Combining logic optimization & mapping is much harder • Academic tools mostly focus on mapping • Problems with current test cases • How far from optimal? • Logic optimization? • Decrease of FPGA synthesis papers • Suggests fewer improvements possible • Why there is a need for new ones • Test specific properties of logic synthesis tools • LEKO & LEKU UCLA VLSICAD LAB

5. Construction Overview (LEKO) • First create a small “core” graph, G5, with a known optimal mapping (and possibly a logic synthesis) solution. • G5 has to have the following properties • 5 inputs (x1,x2,…,x5) • 5 outputs (y1,y2,…,y5) • yi = f (x1,x2,…,x5) • Internal nodes have exactly two inputs. •  optimal (in terms of area/depth) mapping of G5 into a 4-LUT mapping solution with only has 4-LUTs (no 3-LUTs or 2-LUTs). • Why these properties? • Simplest G5 for 4-LUT architecture • Can be cascaded into larger structures UCLA VLSICAD LAB

6. G5 – example (optimal 7 4-LUTs) UCLA VLSICAD LAB

7. Construction Overview (LEKO) • Algorithm Steps • Create a G5 • Then duplicate it and connect them together is such a way s.t. there is a unique traversal of G5’s from PO to PI. • This creates a new graph where we have the following properties: • There exists a known optimal mapping solution • This also provides a tight upper-bound to the optimal logic synthesis solution • By using different G5s we can construct different LEKO networks with any variety of properties. • G5 can have different mapping and logic synthesis solutions • G5 can be based on realistic designs (multipliers, adders, etc) UCLA VLSICAD LAB

8. Construction Examples (LEKO) G5 G5 G5 G5 G5 G5 G5 G5 G5 G5 UCLA VLSICAD LAB

9. Optimality Theorem: The optimal mapping solution of an arbitrarily sized LEKO circuit without logic optimization is achieved when every G5 in the circuit is mapped optimally without overlapping any other G5. Proof Idea: A LUT spanning two layers can will not reduce the area of the solution. This can be easily shown by looking at what would happen to G5 at layer i and at layer i+1 • Complete proof is in the paper UCLA VLSICAD LAB

10. LEKO Examples • LEKO – Logic synthesis Examples with Known Optimals • Naming • G25 has 25 inputs and 25 outputs • Gx has x inputs and x outputs • Tools tested • Altera’s Quartus 5.0, Xilinx’s ISE 7.1i, UCLA’s DAOmap and Berkeley’s ABC • 4-LUT architecture • Area optimization only (NP-hard) UCLA VLSICAD LAB

11. Results (LEKO) • Only mapping needed to produce optimal results. • What do these mean? • Scaled fairly well • Average gap = 15% • Why Quartus and ISE did so well • Performed extra non-mapping steps UCLA VLSICAD LAB

12. Creating LEKU • LEKU – Logic synthesis Examples with Known Upper bounds • Constructed from LEKO G25 (25 inputs and 25 outputs) • Collapse then decompose the graph • Creates much larger graph that is logically equivalent to original • LEKU-CD – collapsed decomposed into AND/OR gates • LEKU-CB – collapsed balanced • LEKU-CD’ • LEKU-CD was too large for Xilinx as a single input • Split LEKU-CD into 25 separate designs, one for each PO UCLA VLSICAD LAB

13. Results on LEKU • Logic Optimization and Mapping were needed • Academic tools were allowed to use preprocessing tools • What does this mean? • There exist designs on which these tool perform very badly • Average gap = 171x • Suggest that all of these tools lack global minimization heuristics UCLA VLSICAD LAB

14. LEKO/LEKU vs Real Designs • Limitations • Whole circuit is combinational logic • Contain highly repeated structures in the original circuits • Doesn’t mean tools are 70x away from optimal on real designs • Different uses than real design • LEKO • Test mapping phase of algorithm • Perform well on current LEKO benchmarks • Will construct larger core graphs  worse results ? • LEKU • Test logic optimization phase of algorithm • Ability to reproduce original structure • Duplication removal • Logic Identification • Other global heuristics UCLA VLSICAD LAB

15. Conclusions • Conclusions • LEKO • Only circuits that test optimality of technology mapping • Have an optimal mapping solution • LEKU • Test global area minimizing heuristics • Have a very tight upper bound on optimal solution • These circuits address a need for specific method testing • Current state of technology • Technology Mapping • Current tools do very well • Overall Logic Synthesis • Current tools just can’t produce good solutions that require a global minimization heuristics. UCLA VLSICAD LAB

16. Conclusions (continued) • Download every testcases mentioned here • http://cadlab.cs.ucla.edu/ • Click on “Optimality Study” • Click on “LEKO/LEKU” • Harder and Larger LEKO and LEKU circuits will be posted soon! • Check out the article in EE Times • Just search EE Times for “kirill” • Thank you EE Times for your interest! http://eetimes.com/showArticle.jhtml?articleID=180204087 • Questions? UCLA VLSICAD LAB

17. Thanks ! UCLA VLSICAD LAB

18. Additional Slides

19. Construction Algorithm (LEKO) UCLA VLSICAD LAB

20. Variations • LEKO • Using larger core graphs to create more complex designs • Using commonly used cells as the core graphs • Using collection of core graphs • LEKU • Using LEKO and adding in specific things to test • Duplicating some specific parts • Adding wires that will be removed when DON’T CARES are computed UCLA VLSICAD LAB

21. Interesting New Results • After seeing the results we got several responses • ABC • Repeating map 4-LUTs  don’t care calculation let to 3x improvement on the largest LEKU example • DAOMap • Multiple iteration of map 5-LUTs  simplify  map 4-LUTs showed similar improvements on the LEKU examples • Altera • For the LEKO the following map 5-LUT  map 4-LUT was able to achieve near optimal solutions • This result wouldn’t extend if we used a larger G5 UCLA VLSICAD LAB

22. Different G5s • Assuming a K-LUT • G5 has to have the following properties • It has m inputs and m outputs. • Every output is a function of all five inputs. • Each internal node of G5 has exactly two inputs. • There exists an optimal (in terms of area/depth) mapping of G5 into a K-LUT mapping solution, denoted M5, such that M5 only has K-LUTs. • Where • m ≥ K + 1 • The larger the m the harder the G5 is to map UCLA VLSICAD LAB