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Logic Synthesis

Outline Logic Synthesis Problem Logic Specification Two-Level Logic Optimization Goal Understand logic synthesis problem Understand logic optimization problem From Hank Walker. Logic Synthesis. Map from logic equations to gate-level combinational logic will consider FSM synthesis later

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Logic Synthesis

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  1. Outline Logic Synthesis Problem Logic Specification Two-Level Logic Optimization Goal Understand logic synthesis problem Understand logic optimization problem From Hank Walker Logic Synthesis

  2. Map from logic equations to gate-level combinational logic will consider FSM synthesis later Goals maximize speed minimize power minimize chip/board area Constraints target technology CAD tool CPU time b b c c d d Logic Synthesis Problem a’bc + abc + d bc + d

  3. Two-level logic equations sum of products “PLA format” “ESPRESSO format” Multiple-level logic equations Berkeley Logic Intermediate Format (BLIF) arbitrary set of equations generated in converting directly from RTL e.g. logic equations for ALU generated from gate-level netlist Logic Specification x = abc’ + def + ghi + jkl + ... y = bc + e’ + ghi + jk + ... .i 3 .o 3 .p 4 10x101 x01100 110110 11x010 .e x = ab’ + b’c + abc’ y = abc’ + ab z = ab’ literal operand x = (a(b+c)d + ef(i+j))(k + l)

  4. Logic equations are flattened to two levels AND-OR, NAND-NAND, NOR-NOR common starting point for most tools eliminates any input bias causes exponential explosion in equation size in worst case does not occur in practice Logic Specification • • • • • • • • •

  5. 1. logic equation simplification reduce literal and operand count less “stuff” to implement generally reduces chip area does not always minimize delay 2. logic synthesis map equations to generic gates AND, OR, NOT 3. gate-level optimization “local” transformations for speed, area, power e.g. AND-NOT => NAND need estimate of technology costs 4. technology mapping map from gates to component library FPGAs, standard cells, TTL, etc. Logic Synthesis Problem

  6. Build map - 2N entries label entries 0 - F = 0 1 - F = 1 X - F = don’t care Find minimumprime cover cover - set of terms whose union is true for all entries that are 1 can also cover all 0 entries instead and complement F prime - terms are simplest (largest cover) they can be AB vs. ABC + ABC’ minimum - fewest terms Karnaugh Maps - Two-Level Minimization F = A’BC’D + A’BCD + ABC’D’ + ABC’D + ABCD + ABCD’ + AB’C’D’ + AB’C’D C 0 0 0 0 0 1 1 0 B 1 1 1 1 A 1 1 0 0 D F = AB + AC’ + BD F’ = A’B’ + B’C + A’D’

  7. Examples C C 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 B B 1 1 1 1 1 1 1 1 A A 1 1 0 0 1 1 0 0 D D F = AC’ + BD F = AC’ + BD + ABCD’ F is not a cover ABCD’ is not prime

  8. Examples C C 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 B B 1 1 1 1 1 1 1 1 A A 1 1 0 0 1 1 X X D D F’ = A’B’ + A’D’ + B’C F = A + BD Solve for complement Use don’t care terms when determining if term is prime

  9. Can Get Into Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D

  10. Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D

  11. Solution try different cover sequences Minimum cover is NP-complete exponential time in worst case Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D F = BD’ + A’D’ + A’B’ F = A’B’ + BD’ Result is not minimal Result is minimal Usually many minima

  12. Exponential space in number of inputs e.g. 100 input function needs 2100 cells very inefficient if number of 1 or 0 cells is small Needs of two-level minimization efficient data structure ideally linear in size of function efficient means of searching for minimal prime cover get close to optimal in reasonable time serve as a building-block for multi-level minimization Problems with Karnaugh Maps

  13. N-dimensional boolean space - 2N points, each associated with a unique set of N literals e.g. entries in a Karnaugh map or truth table each point is a minterm e.g. abcd, ab’cd, in space <a:d> cube - conjunction (AND) of literals in N-dim boolean space points on N-dim hypercube that are 1 examples: a’bc, acd expression - disjunction (OR) of cubes, i.e. equation example: a’bc + def don’t cares - missing literals from cube example: abc in space of <a:d>, d is don’t care result is cube covering larger part of space abc = abcd’ + abcd Logic Optimization Definitions cube: a’ DC: b a’b ab space: <a:b> a’b’ ab’

  14. Approach find minimal set of cubes to cover ON-set (1 minterms) each cube = AND gate minimal cubes => minimal AND gates each expression = cubes + OR gate one expression (OR gate) per output exploit don’t cares to increase cube sizes each DC doubles cube size cube must only cover 1 or DC vertices or cover OFF-set (0 minterms) instead ON DC OFF Two-Level Logic Optimization a’b ab redundancy in cube cover a’ + b a’b’ ab’

  15. Minimal set of cubes minimum graph covering problem NP-complete - exponential in worst case must use heuristic search Complications solve simultaneously for each expression (output) minimize total number of unique cubes consider ON vs. OFF vs. DON’T CARE set Two-Level Logic Optimization ESPRESSO input ESPRESSO output .i 3 .o 3 .p 4 10x101 x01100 110110 11x010 .e .i 3 .o 3 .p 4 -01 100 11- 010 1-0 100 10- 001 .e x = b’c + ac’ y = ab z = ab’ x = ab’ + b’c + abc’ y = abc’ + ab z = ab’

  16. Approach minimize cover of ON-set of function ON-set is set of vertices for which expression is TRUE minimum set of cubes exploit don’t cares to increase cube sizes Algorithm start with cubes covering the ON-set this is just sum-of-products form iteratively expand, shrink, add, remove cubes remove redundant (covered) cubes result is irredundant cover Two-Level Logic Optimization x = a’ + b x = a’b + ab + a’b’ a’b ab a’b ab a’b’ ab’ a’b’ ab’

  17. ESPRESSO Algorithm • Forig = ON-set; /* vertices with expression TRUE */ • R = OFF-set; /* vertices with expression FALSE */ • D = DC-set; /* vertices with expression DC */ • F = expand(Forig, R); /* expand cubes against OFF-set */ • F = irredundant(F, D); /* remove redundant cubes */ • do { • do { • F = reduce(F, D); /* shrink cubes against ON-set */ • F = expand(F, R); • F = irredundant(F, D); • } until cost is “stable”; • /* perturb solution */ • G = reduce_gasp(F, D); /* add cubes that can be reduced */ • G = expand_gasp(G, R); /* expand cubes that cover another */ • F = irredundant(F+G, D); • } until time is up; • ok = verify(F, Forig, D); /* check that result is correct */

  18. Expand expand essentialcubes in F in decreasing size to a prime cube prime cube - fully expanded against OFF-set essential cube - contains essential vertex essential vertex - minterm no other cube covers remove any covered cubes ON 01 11 DC 00 10 OFF Cube Operations 01 11 Expand 00 10

  19. Irredundant find minimal cover with each cube containing an essential vertex find relatively essential cubes E removing them violates cover - keep them redundant cubes R = F - E can be individually removed totally redundant Rt - covered by E+D remove Rt partially redundant Rp - R - Rt new F = E + minimal set of Rp ON DC OFF Cube Operations E 01 11 01 11 Rp Rt Irredundant 00 10 00 10 Rp

  20. Reduce shrink cubes in descending order of size while maintaining cover smaller cubes can expand in more directions smaller cubes more likely to be covered by other cubes during expansion ON 01 11 01 11 DC 00 10 00 10 OFF Cube Operations Reduce

  21. Reduce Gasp for each cube add a subcube not covered by other cubes Expand Gasp expand subcubes and add them if they cover another cube later use Irredundant to discard redundant cubes this is a “last gasp” heuristic for exploration no ordering by cube size ON DC OFF Cube Operations 01 11 01 11 Reduce Gasp 00 10 00 10 01 11 01 11 Expand Gasp 00 10 00 10

  22. Example x = a’b + ab + a’b’ Expand a’b ab a’b ab a’b’ ab’ a’b’ ab’ Irredundant Reduce a’b ab a’b ab a’b’ ab’ a’b’ ab’ Expand x = a’ + b a’b ab Irredundant a’b ab a’b’ ab’ a’b’ ab’ Cost Stable

  23. Examples E Rp Rp E Prime & Irredundant Cover Essential and Redundant Cubes Initial Cover Reduce Expand in right direction

  24. Experimental Results ESPRESSO algorithm gets minimum or close to minimum cover where cover is known up to 10 000 input literals, 100 inputs, 100 outputs tested CPU time < 12 min on high-speed workstation Application PLA minimization use as subroutine in multi-level logic minimization minimize pieces of larger circuit Conclusions

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