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San Jose State University Department of Electrical Engineering May 10th, Spring 2002

San Jose State University Department of Electrical Engineering May 10th, Spring 2002. 8-BIT FULL ADDER WITH FEEDBACK. EE SENIOR DESIGN PROJECT 198B Advisor: Prof. David Parent Group Members Dong Tieu, Liem Ho, Hau Do. Presentation Overview. Introduction Team Goal Design Principle

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San Jose State University Department of Electrical Engineering May 10th, Spring 2002

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  1. San Jose State UniversityDepartment of Electrical EngineeringMay 10th, Spring 2002 8-BIT FULL ADDER WITH FEEDBACK EE SENIOR DESIGN PROJECT 198B Advisor: Prof. David Parent Group Members Dong Tieu, Liem Ho, Hau Do

  2. Presentation Overview • Introduction • Team Goal • Design Principle • Specifications • Results and Accomplishments • Future & Recommendations • Conclusion

  3. Introduction • Specification: • Speed: 25 MHz • Area: 1000 X 1000 um • Rising time and Falling time: 10 ns • Capable load: 10 pF • Propagation Time: 15 ns

  4. Introduction • The Solution • Use AMI 1.6 um Technology of Cadence Software • to implement. • Conduct MOSIS for a free fabrication. • Use DPS Analyzer to test.

  5. Introduction • Motivations • Familiar with design environment • Allow our design to be used in school environment. • Let’s future students to think about using all resources available at our school.

  6. Team Project • Team Goal • Apply AMI 1.6 um technology. • Provide good samples for future use. • Meet Specs • Finish on time.

  7. Design Principle • Block Diagram

  8. Design Flow Chart

  9. 8-Bit Full Adder Schematic

  10. 8-Bit Full Adder Layout

  11. 8-Bit Full Adder Waveform

  12. D Flip-Flop Schematic

  13. D Flip-Flop Layout

  14. D Flip-Flop Waveform

  15. Super Buffer Schematic 4 / 4 4 / 4 36 / 16 140/52

  16. Super Buffer Layout

  17. Super Buffer Propagating Time

  18. 8-Bit Shift Register Schematic

  19. 8-Bit Shift Register Layout

  20. 8-Bit Shift Register Propagating Time

  21. Completed Device Schematic

  22. Completed Device Layout

  23. Ready to Fabricate

  24. Cost • Project Cost • Cadence software available at SJSU. • Free fabrication from MOSIS. • DSP Analyzer provided by Dr. Parent • Total cost: $0.00 & 1000 working hrs.

  25. Future Improvement and Outlook • Improvement • Speed • - Use “Look ahead carry in” method. • - Use “Dynamic” method. • - Use “0.2 um or 0.3 um Technology”. • Decrease Chip’s Area • Increase Load capacity • Reduce Power consumption

  26. Conclusion • What has been achieved? • Area: 650 X 800 um • Propagating Time: 10 ns • Speed: > 25 MHz • Rising time and Falling time: 5 ns • Capable load: 10 pF

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