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CpE 442 Computer Architecture and Engineering Designing Single Cycle Control

CpE 442 Computer Architecture and Engineering Designing Single Cycle Control

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CpE 442 Computer Architecture and Engineering Designing Single Cycle Control

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  1. CpE 442Computer Architecture and EngineeringDesigning Single Cycle Control

  2. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions (10 minutes) • Control signals for Load, Store, Branch, & Jump (15 minutes) • Building a local controller: ALU Control (10 minutes) • The main controller (20 minutes) • Summary (5 minutes)

  3. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits Recap: The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination registers specifier • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction

  4. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits Recap: The MIPS Subset • ADD and subtract • add rd, rs, rt • sub rd, rs, rt • OR Imm: • ori rt, rs, imm16 • LOAD and STORE • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16 • JUMP: • j target

  5. Recap: A Single Cycle Datapath • We have everything except control signals (underline) • Today’s lecture will show you how to generate the control signals Instruction<31:0> Branch Instruction Fetch Unit Jump Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  6. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now? • The Five Classic Components of a Computer • Today’s Topic: Designing the Control for the Single Cycle Datapath

  7. The Steps of Designing a Processor • 0) Instruction Set Architecture => • Register Transfer Language Program • Convert each instruction to RTL statements • Register Transfer Language program => Datapath Design • Determine Datapath components • Determine Datapath interconnects • Datapath components => Control signals • Control signals => Control logic => Control • Unit Design

  8. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions • Control signals for Load, Store, Branch, & Jump (15 minutes) • Building a local controller: ALU Control (10 minutes) • The main controller (20 minutes) • Summary (5 minutes)

  9. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The ADD Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  10. 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the Beginning of Add / Subtract • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = previous Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch = previous Zero = previous

  11. 31 26 21 16 11 6 0 op rs rt rd shamt funct The Single Cycle Datapath during Add and Subtract • R[rd] <- R[rs] + / - R[rt] Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 1 1 0 Mux ALUctr = Add or Subtract Rt Rs Rd Imm16 Rs Rt RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  12. 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the End of Add and Subtract • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = 0 Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch = 0 Zero = x

  13. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Or Immediate • R[rt] <- R[rs] or ZeroExt[Imm16] Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 0 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = Or RegWr = 1 MemtoReg = 0 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 0

  14. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions (10 minutes) • Control signals for Load, Store, Branch, & Jump • Building a local controller: ALU Control (10 minutes) • The main controller (20 minutes) • Summary (5 minutes)

  15. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Load • R[rt] <- Data Memory {R[rs] + SignExt[imm16]} Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 0 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 MemtoReg = 1 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory Extender 32 imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  16. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = x 1 0 Mux ALUctr = Add Rt Rs Rd Imm16 Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 1 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 32 Data In Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 1

  17. 31 26 21 16 0 op rs rt immediate The Single Cycle Datapath during Branch • if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 Instruction<31:0> Branch = 1 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = x 1 0 Mux ALUctr = Subtract Rt Rs Rd Imm16 Rs Rt RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x

  18. 31 26 21 16 0 op rs rt immediate 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the End of Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = 0 Instruction<31:0> 30 SignExt 30 imm16 16 Assume Zero = 1 to see the interesting case. Instruction<15:0> Branch = 1 Zero = 1

  19. 31 26 0 op target address The Single Cycle Datapath during Jump • Nothing to do! Make sure control signals are set correctly! Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 1 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = x 1 0 Mux Rt Rs Rd Imm16 ALUctr = x Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = x ExtOp = x

  20. 31 26 0 op target address 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the End of Jump • PC <- PC<31:29> concat target<25:0> concat “00” 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = 1 Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch = 0 Zero = x

  21. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 Branch 0 0 0 0 0 1 0 Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add xxx Subtract 31 26 21 16 11 6 0 op rs rt rd shamt funct immediate op rs rt op target address A Summary of the Control Signals See func 10 0000 10 0010 We Don’t Care :-) Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type add, sub I-type ori, lw, sw, beq J-type jump

  22. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions (10 minutes) • Control signals for Load, Store, Branch, & Jump (15 minutes) • Building a local controller: ALU Control • The main controller (20 minutes) • Summary (5 minutes)

  23. op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop<N:0> “R-type” Or Add Add xxx Subtract ALU Control (Local) The Concept of Local Decoding func ALUctr op 6 Main Control 3 ALUop 6 N ALU

  24. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N The Encoding of ALUop • In this exercise, ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01

  25. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N R-type ori lw sw beq jump ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 xxx 0 01 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation 10 0000 add 000 Add 10 0010 subtract 001 Subtract 10 0100 and 010 And ALU 10 0101 or 110 Or 10 1010 set-on-less-than 111 Set-on-less-than The Decoding of the “func” Field

  26. R-type ori lw sw beq ALUop (Symbolic) “R-type” Or Add Add Subtract ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 ALUop func ALU Operation ALUctr bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> 0 0 0 x x x x Add 0 1 0 0 x 1 x x x x Subtract 1 1 0 0 1 x x x x x Or 0 0 1 1 x x 0 0 0 0 Add 0 1 0 1 x x 0 0 1 0 Subtract 1 1 0 1 x x 0 1 0 0 And 0 0 0 1 x x 0 1 0 1 Or 0 0 1 1 x x 1 0 1 0 Set on < 1 1 1 The Truth Table for ALUctr funct<3:0> Instruction Op. 0000 add 0010 subtract 0100 and 0101 or 1010 set-on-less-than

  27. The Logic Equation for ALUctr<2> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2> • ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> 0 x 1 x x x x 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1 This makes func<3> a don’t care

  28. The Logic Equation for ALUctr<1> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1> • ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0> 0 0 0 x x x x 1 0 x 1 x x x x 1 1 x x 0 0 0 0 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1

  29. The Logic Equation for ALUctr<0> ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0> • ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0> 0 1 x x x x x 1 1 x x 0 1 0 1 1 1 x x 1 0 1 0 1

  30. func ALU Control (Local) 6 ALUctr ALUop 3 3 The ALU Control Block • ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> • ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0> • ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

  31. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions (10 minutes) • Control signals for Load, Store, Branch, & Jump (15 minutes) • Building a local controller: ALU Control (10 minutes) • The main controller • Summary (5 minutes)

  32. RegDst func ALUSrc ALUctr ALU Control (Local) op 6 Main Control : 3 6 ALUop 3 The “Truth Table” for the Main Control op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop <2> 1 0 0 0 x 0 ALUop <1> 0 1 0 0 x 0 ALUop <0> 0 0 0 0 x 1

  33. . . . . . . op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump The “Truth Table” for RegWrite op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump • RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) RegWrite 1 1 1 x x x RegWrite

  34. . . . . . . op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump PLA Implementation of the Main Control RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0>

  35. Outline of Today’s Lecture • Recap and Introduction (10 minutes) • Control for Register-Register & Or Immediate instructions (10 minutes) • Control signals for Load, Store, Branch, & Jump (15 minutes) • Building a local controller: ALU Control (10 minutes) • The main controller (20 minutes) • Summary

  36. Putting it All Together: A Single Cycle Processor ALUop ALU Control ALUctr 3 RegDst func op 3 Main Control Instr<5:0> 6 ALUSrc 6 : Instr<31:26> Instruction<31:0> Branch Instruction Fetch Unit Jump Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Instr<15:0> Clk ALUSrc ExtOp

  37. Worst Case Timing Clk Clk-to-Q Old Value New Value PC Instruction Memoey Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value ExtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value Register Write Occurs RegWr Old Value New Value Register File Access Time busA Old Value New Value Delay through Extender & Mux busB Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New

  38. Drawback of this Single Cycle Processor • Long cycle time: • Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew • Cycle time is much longer than needed for all other instructions