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EEM 486 : Computer Architecture Lecture 3 Designing Single Cycle Control

EEM 486 : Computer Architecture Lecture 3 Designing Single Cycle Control. Processor. Input. Control. Memory. Datapath. Output. The Big Picture: Where are We Now?. ALU. PC. Clk. An Abstract View of the Implementation. Control. Ideal Instruction Memory. Control Signals. Conditions.

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EEM 486 : Computer Architecture Lecture 3 Designing Single Cycle Control

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  1. EEM 486: Computer ArchitectureLecture 3Designing Single Cycle Control

  2. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now?

  3. ALU PC Clk An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32 Datapath

  4. Instruction<31:0> nPC_sel Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr Zero 5 5 5 MemWr MemtoReg busA Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp Recap: A Single Cycle Datapath • We have everything except control signals (underline)

  5. nPC_MUX_sel Inst Memory Adr 4 00 PC Adder Mux Clk imm16 PC Ext Adder Recap: Meaning of the Control Signals • nPC_MUX_sel: 0PC <– PC + 4 1PC <– PC + 4 + SignExt(Im16) || 00

  6. Equal MemWr Rt ALUctr MemtoReg Rd RegDst 0 1 Rs Rt RegWr 5 5 5 busA = Rw Ra Rb busW 32 32 32-bit Registers ALU 0 32 busB 32 0 32 Mux Mux Clk 32 WrEn Adr 1 Data In 1 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp Recap: Meaning of the Control Signals • MemWr: 1  write memory • MemtoReg: 0  ALU; 1  Mem • RegDst: 0  “rt”; 1  “rd” • RegWr: 1  write register • ExtOp: “zero”, “sign” • ALUsrc: 0  regB; 1  immed • ALUctr: “add”, “sub”, “or”

  7. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  8. Inst Memory Instruction<31:0> Adr nPC_MUX_sel 4 Adder 00 0 Mux PC 1 Adder Clk imm16 Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • Same for all instructions

  9. Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst = 1 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = Add RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr=0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc=0 ExtOp = x The Single Cycle Datapath During Add • R[rd] <- R[rs] + R[rt]

  10. Inst Memory Instruction<31:0> Adr nPC_MUX_sel 4 Adder 0 00 Mux PC 1 Adder Clk imm16 Instruction Fetch Unit at the End of Add • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump

  11. Instruction<31:0> nPC_sel = Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp = The Single Cycle Datapath During Or Immediate • R[rt] <- R[rs] or ZeroExt[Imm16] RegDst =

  12. Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst = 0 1 0 Mux ALUctr=Add Rt Rs Rd Imm16 Rs Rt RegWr = 1 MemtoReg = 1 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 1 WrEn Adr 1 Data In 32 Data Memory 32 Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 1 The Single Cycle Datapath During Load • R[rt] <- Data Memory [ R[rs] + SignExt[imm16] ]

  13. Instruction<31:0> nPC_sel = Instruction Fetch Unit Rd Rt <0:15> <21:25> <16:20> <11:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr = RegWr = 5 5 5 MemtoReg = busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp = The Single Cycle Datapath During Store • Data Memory [ R[rs] + SignExt[imm16] ] <- R[rt]

  14. Instruction<31:0> nPC_sel= +4 Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst = x 1 0 Mux Rt Rs Rd Imm16 ALUctr= Add Rs Rt RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 1 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 32 Data In Data Memory Extender imm16 32 16 Clk ALUSrc = 1 ExtOp = 1 The Single Cycle Datapath During Store

  15. Instruction<31:0> nPC_sel= “Br” Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst = x 1 0 Mux Rt Rs Rd Imm16 Rs Rt ALUctr=Sub RegWr = 0 5 5 5 MemtoReg = x busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x The Single Cycle Datapath During Branch • if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

  16. Instruction<31:0> Inst Memory nPC_sel Zero Adr nPC_MUX_sel 4 0 00 Adder PC 1 Mux Clk imm16 Adder Instruction Fetch Unit at the End of Branch • What is encoding of nPC_sel? • Direct MUX select? • Branch / not branch

  17. Step 4: Given Datapath: RTL -> Control Instruction<31:0> Inst Memory <11:15> <21:25> <0:15> <21:25> <16:20> Adr Op Fun Rt Rs Rd Imm16 Control ALUctr nPC_sel RegWr RegDst ExtOp ALUSrc MemWr MemtoReg Zero DATA PATH

  18. Summary of Control Signals inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr,nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rt]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– [PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

  19. We Don’t Care :-) See func 10 0000 10 0010 Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 add sub ori lw sw beq RegDst 1 1 0 0 x x ALUSrc 0 0 1 1 1 0 MemtoReg 0 0 0 1 x x RegWrite 1 1 1 1 0 0 MemWrite 0 0 0 0 1 0 nPCsel 0 0 0 0 0 1 x x 1 x 0 1 ExtOp Add Sub ALUctr<2:0> Add Or Add Sub Summary of the Control Signals

  20. func ALUctr ALU Control (Local) op 6 Main Control 3 ALUop 6 N ALU Concept of Local Decoding op 00 0000 00 1101 10 0011 10 1011 00 0100 R-type ori lw sw beq RegDst 1 0 0 x x ALUSrc 0 1 1 1 0 MemtoReg 0 0 1 x x RegWrite 1 1 1 0 0 MemWrite 0 0 0 1 0 0 0 0 0 1 Branch x 1 1 x 0 ExtOp ALUop<N:0> “R-type” Or Add Add Sub

  21. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N R-type ori lw sw beq ALUop (Symbolic) “R-type” Or Add Add Sub ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 Encoding of ALUop • In this exercise, ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, and (4) Subtract • To implement the full MIPS ISA, ALUop has to be 3 bits to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform: • (2) Or, (3) Add, (4) Subtract,(5) And, and (6) Xor

  22. func ALU Control (Local) op 6 ALUctr Main Control ALUop 6 3 N 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation 10 0000 add 000 And 10 0010 subtract 001 Or 10 0100 and R-type ori lw sw beq 010 Add ALU 10 0101 ALUop (Symbolic) or “R-type” Or Add Add Sub 110 Subtract 10 1010 ALUop<2:0> set-on-less-than 1 00 0 10 0 00 0 00 0 01 111 Set-on-less-than Decoding of the “func” Field

  23. funct<3:0> Instruction Op. 0000 add R-type ori lw sw beq 0010 subtract ALUop (Symbolic) “R-type” Or Add Add 0100 and Sub ALUop<2:0> 1 00 0 10 0 00 0 00 0101 or 0 01 ALUop func ALU Operation ALUctr 1010 set-on-less-than bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> bit<2> bit<1> bit<0> 0 0 0 x x x x Add 0 1 0 0 x 1 x x x x Subtract 1 1 0 0 1 x x x x x Or 0 0 1 1 x x 0 0 0 0 Add 0 1 0 1 x x 0 0 1 0 Subtract 1 1 0 1 x x 0 1 0 0 And 0 0 0 1 x x 0 1 0 1 Or 0 0 1 1 x x 1 0 1 0 Set on < 1 1 1 Truth Table for ALUctr

  24. ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2> 0 x 1 x x x x 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1 This makes func<3> a don’t care Logic Equation for ALUctr<2> ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

  25. ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1> 0 0 0 x x x x 1 0 x 1 x x x x 1 1 x x 0 0 0 0 1 1 x x 0 0 1 0 1 1 x x 1 0 1 0 1 Logic Equation for ALUctr<1> ALUctr<1> = !ALUop<2> & !ALUop<1> + !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & !func<0>

  26. ALUop func bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0> 0 1 x x x x x 1 1 x x 0 1 0 1 1 1 x x 1 0 1 0 1 Logic Equation for ALUctr<0> ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

  27. func ALU Control (Local) 6 ALUctr ALUop 3 3 ALU Control Block ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> ALUctr<1> = !ALUop<2> & !ALUop<1> +!ALUop<2> & ALUop<0> ALUop<2> & !func<2> & !func<0> ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

  28. Step 5: Logic For Each Control Signal • nPC_sel <= if (OP == BEQ) then “Br” else “+4” • ALUsrc <= if (OP == “Rtype”) then “regB” else “immed” • ALUctr <= if (OP == “Rtype”) then functelseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” • ExtOp <= _____________ • MemWr <= _____________ • MemtoReg <= _____________ • RegWr: <=_____________ • RegDst: <= _____________

  29. RegDst func ALUSrc ALUctr ALU Control (Local) op 6 Main Control : 3 6 ALUop 3 op 00 0000 00 1101 10 0011 10 1011 00 0100 R-type ori lw sw beq RegDst 1 0 0 x x ALUSrc 0 1 1 1 0 MemtoReg 0 0 1 x x RegWrite 1 1 1 0 0 MemWrite 0 0 0 1 0 nPC_sel 0 0 0 0 1 1 x 1 ExtOp 0 x ALUop (Symbolic) “R-type” Or Add Add Subtract ALUop <2> 1 0 0 0 0 ALUop <1> 0 1 0 0 0 ALUop <0> 0 0 0 0 1 “Truth Table” for the Main Control

  30. op 00 0000 00 1101 10 0011 10 1011 00 0100 R-type ori lw sw beq RegWrite 1 1 1 0 0 . . . . . op<5> op<5> op<5> op<5> op<5> . . . . . <0> <0> <0> <0> <0> R-type ori lw sw beq RegWrite “Truth Table” for RegWrite RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)

  31. op<5> op<5> op<5> op<5> op<5> . . . . . <0> <0> <0> <0> <0> R-type ori lw sw beq RegWrite ALUSrc RegDst MemtoReg MemWrite Branch ExtOp ALUop<2> ALUop<1> ALUop<0> PLA Implementation of the Main Control . . . . .

  32. ALUop ALU Control ALUctr 3 RegDst func Instr<31:26> 3 Main Control Instr<5:0> op 6 ALUSrc 6 : Instruction<31:0> nPC_sel Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Instr<15:0> Clk ALUSrc ExtOp Putting it All Together: A Single Cycle Processor

  33. Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers ALU PC Data In Next Address B Clk Clk 32 Clk Recap: An Abstract View of the Critical Path (Load) Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

  34. Worst Case Timing (Load) Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value ExtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value Register Write Occurs RegWr Old Value New Value Register File Access Time busA Old Value New Value Delay through Extender & Mux busB Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New

  35. Drawback of this Single Cycle Processor • Long cycle time: • Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew • Cycle time for load is much longer than needed for all other instructions

  36. Processor Input Control Memory Datapath Output Summary • Single cycle datapath => CPI=1, CCT => long • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Control is the hard part • MIPS makes control easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates

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