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The TEL62 experience

This document outlines the status and progress of the TEL62 hardware and firmware as discussed at the NA62 TDAQ Working Group meeting in Siena on August 30, 2012. Key highlights include the distribution of TEL62 boards, results of dry run tests, and challenges faced at CERN. November and July evaluations ensured several boards are operational, while others require repair. Attention was drawn to the importance of careful handling during transport to avoid hardware issues. Compliance with firmware updates and data flow tests were prioritized in preparation for the upcoming technical run.

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The TEL62 experience

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  1. The TEL62 experience Bruno Angelucci INFN & University of Pisa NA62 TDAQ WG meeting – Siena, 30/08/2012

  2. Outline • TEL62 hardware status • TEL62 boards distribution • TEL62 firmware status • TEL62 dry run tests • Towards the technical run

  3. Hardware status • 14 V2 boards arrived in Pisa at beginning of July for preliminary tests before delivering at CERN. • 3 boards perfectly working • 8 boards with several “little” problems solved in Pisa • 3 boards sent back to mounting firm • After 10 days of hard work in Pisa, 11 boards perfectly working delivered at CERN. • New hardware issues found out at CERN: bad transport… or bad handling… or else? Please “handle with care”! • Additional work done in CERN new electronic lab but not all the problems have been solved

  4. Boardsdistribution

  5. Boards distribution and cabling MUV LAV

  6. Boards distribution and cabling CEDAR CHOD

  7. Boardslogistic OK OK OK OK OK NO NO NO • 3 boards at ARTEL and 2 in Pisa to be repaired: • 1 for STRAW • 1 for possible use with TALK (now using TELL1) • 2 for LKr/L0 • 1 spare

  8. TEL62 firmware - PP

  9. TEL62 firmware - SL

  10. Dry run TEL62 tests • TTC interface using LTU in standalone mode • fiber cabling and clock distribution • choke and error lines • trigger counting (A channel) • trigger type decoding (B channel) • timestamp spacing • PP buffers using detector FEE and TDCB • Data merging from 4 IB to 1 OB • Data monitoring (using fake TDC data)

  11. Dry run TEL62 tests • TTC interface using TALK and LTU in global mode, and using 7 TEL62 • trigger counting • trigger type decoding • synchronization • start of burst • end of burst • physics triggers (data extracted from DDR, stop in the SL IB, bug understood) • packet extraction, merging in pc farm, storage (for all triggers but the physics triggers)

  12. Towards the technical run • Complete the distribution of the repaired boards. Please contact us for every problem found using the TEL62: all boards must work perfectly before the beginning of technical run • Firmware: • firmware uploading: refinement of jbi player needed • complete corrections to data format (physics triggers) • fix in the SL to complete data flow from DDR to storage, after receiving physics trigger • decide “what to do” after the EOB signal arrives • secondary priority: other ways to read the DDR (triggers not from primitives or triggerless mode for debug) could be useful? • Test: • re-test the data flow from DDR extraction to farm, with fake data and then pulsing the front-end • test the trigger flow to the GBE • simulate a real run to test the entire chain TALK-LTU-TEL62, also using run control

  13. Spares

  14. TEL62 boards test • jtagchain • FPGA programming • EPCS64 programming • board EEPROM programming • DDR test • QDR test • GBE interface test • TTC interface test • PP  SL communication test • TDCB  PP communication test (200pin conn.)

  15. TEL62 firmware – SL trigger

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