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TEL62 update

TEL62 update

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TEL62 update

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  1. TEL62 update Franco Spinella for the TEL62 TEAM INFN-Pisa CERN- TDAQ WG

  2. TEL62 … hardware • 15 produced in 2012. • Some had assembly problems, a couple broke in the following months. • Up to now: • 15 +1 (V1 upgraded to V2) produced • 11 OK • 5 needs repair (FPGA solder/resolder) • Under repair this week. Will be back in Pisafor testing around June 10. • Planned some joint tests with A. Salamon to verify JTAG BST test system. • Will be distributed immediately after.

  3. TEL62 … new DCDC • DCDCs on the board heats a lot • We want to test more efficient DCDC converters • Designed a plug-in to install in the space occupied by actual DCDCs (1.1, 1.8,2.5 V) • No TEL62 PCB modifications required • First tests on the bench OK for 1.8 & 2.5. • 1.1 V has a small design problem, needs a rework or a new board

  4. TEL62 firmware 1 • Huge amount of mods after last report: • Optimized the data transfer toward the TDCB • Clock frequency raised to 160 MHz almost everywhere (no QDR no Gbit) • Added timing constraints for the fitter: now works every recompile … • Solved the reset problem in the Gbit • …

  5. Toward firmware V2 • Trigger performances are below the requirements (1MHz) • ~ 700 KHz with no data from TDCb (empty events) • See Roberto’s talk for details • The bottleneck is related to the DDR2 R/W • We need to optimize the firmware to gain ~ a factor 2 • A new readout scheme (firmware V2) has been defined and partially implemented in VHDL

  6. Actual dataflow: DDR write DDR2 SRAM 3 1 0 2 0 0 0 0 0 3 6.4 us 1 1 • Double buffer: we have 6.4 us to transfer data to DDR2 and servetriggers • DDR2 write latency: 3 Clocks (T=6.2 ns) • Each “slot” is copied independently (empties are skipped …) • At test beam some detectors had data sparsed in all slots … • Write time: • 3 x 6.2 x 257 ~ 5 us (latency) + • data write time + refresh • => Too few time for trigger readout tdcb 2 2 3 3 255 255

  7. Actual dataflow: DDR read DDR2 3 1 0 2 I 0 0 0 0 3 1 Trigger timestamp II 2 • Max trigger freq = 1MHz (1 each us) • DDR2 read latency: 33 Clocks (T= 6.2 ns) • When a trigger timestamp arrives: • 1) Read counters • 2) Read slots (max 3) in a single access, even if empty or almost empty (48 cycles) • 33 x 6.2 x 2 + 48 *6.2 ~ 0.7 us • So at full speed 70 % of time is needed by triggers 3 255

  8. New dataflow: DDR write DDR2 ADDRESS RAM SRAM I COMPRESSOR RAM 4 4 7 7 0 6.4 us 6.4 us • A compressor stage is added • 6.4 us more latency (compare to 1ms trigger latency) • Only 2 DDR2 write access needed • Write time: • 3 x 6.2 x 2 ~ 30 ns (latency) + • data write time + refresh • => Big gain 7 7 7 10 6.4 us 1 tdcb 2 3 255 - VHDL ready & simulated ~ almost tested (some bugs)

  9. New dataflow: DDR read DDR2 ADDRESS RAM • Max trigger freq = 1MHz (1 each us) • DDR2 read latency: 33 Clocks (T= 6.2 ns) • When a trigger timestamp arrives: • 1) Read address (1 access, 2 words) • 2) Read data in a single access ( ~ can be 2 … ) all read words are “good” … • 33 x 6.2 x 2 + n *6.2 ~ 0.3 us + … • NO MORE 3 SLOTS LIMIT (32 or 64 …) 4 4 7 7 7 7 7 10 II Trigger timestamp I - VHDL work in progress …