1 / 25

TEL62 firmware status

TEL62 firmware status. Bruno Angelucci NA62 TDAQ WG Meeting – CERN, 28/03/12. TEL62 firmware progress. Lots of work has been done in Pisa since last meeting (mainly external connections tests), with several parts added or enlarged . Firmware upload: JAM player finally OK!

dorothy-harding
Télécharger la présentation

TEL62 firmware status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. TEL62 firmware status Bruno Angelucci NA62 TDAQ WG Meeting – CERN, 28/03/12

  2. TEL62 firmware progress • Lots of work has been done in Pisa since last meeting (mainly external connections tests), with several parts added or enlarged. • Firmware upload: JAM player finally OK! (many thanks to CristianoSantoni) • “Live” firmware stored at CERN under SVN, with concurrent development (already in use): • well defined library structure: pp,sl,tel62 common entities, top fpga projects, test benches; subdetectors specific stuff. • Some guidelines changed wrt last meeting: more firmware blocks controlled by Pisa group, some blocks deferred to 2013. • Self- consistent and working firmware needed by June, to be used for the dry run.

  3. JAM Player report (Cristiano Santoni, Perugia) • Tosolve the problemof the JAM player the first thingdonewasto update the libraries: installingjtaglib_2.4.2 the JAM Player seemsto work fine evenif the timerequiredtoprogram the EPC16 isstill long. • Weare abletoconfigureboth the EPC16 and directly the FPGAs. • Nowwe are workingtomake the JAM Player windows code consistentwith the linux portingtoachieve the same performance. • Belowwe report the timeneededtoprogram the EPC16 usingtwodifferentfirmware: oneverysimplewichturns on some LEDswhile the otheris the firmware TDCTESTv132: • led.jam: about17m • TDCTESTv132.jam: about60m • Mytests in Pisa usingjtaglib_2.2: • JAM player • TELL1: no success programming EPC16, ok configuring the FPGAsdirectly. • TEL62: ok configuring the FPGAsdirectly, ok programming EPCS64 (~40m). • TDCB: no success programming EPCS64, ok configuring the FPGA directly. • JBI player • TEL62: ok programming EPCS64 (~8m) • TDCB: ok programming EPCS64 (~5m)

  4. TEL62 DDR Daughtercard (TDCB) PP0 DDR CCPC(CPU) GLUE Daughtercard (TDCB) PP1 QDR DDR SL TTCrx Daughtercard (TDCB) PP2 AUX Quad GbE DDR Daughtercard (TDCB) PP3

  5. TEL62 firmware at last meeting STARTED STARTED ADVANCED STARTED (external connections test) STARTED(FOR RICH) STARTED (external connections test) ADVANCED

  6. TEL62 firmware now ADVANCED ADVANCED ADVANCED ADVANCED STARTED Gbithandling ADVANCED Data correction STARTED (external connections test) ADVANCED STARTED(FOR RICH) STARTED(FOR LAV)

  7. Registers and monitoring (documentation)

  8. PP firmware 256 32 PP Franco ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 ? ECS • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests ALTERADDR controller = FIFO 32 Franco 32 40 MHz ? = 2012 32 ? = 2013 32 160 MHz • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 160 MHz 32 ? 32 32 32? 32 ? 32 ? 32 ? 160 MHz 32 32 • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO • Data Write Formatter • write data and addr/count FIFO • Split data in pages • Prepare error log pages • Write data and addr/count FIFOs 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) 32 • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors SL Marco 32 120 MHz ? 32 Franco 160 MHz 160 MHz • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 32 8 SL • Data monitor log data and addr/count FIFO • Monitor TDC data and errors and prepare histograms • Monitor L0 primitives and prepare histograms • Monitor received triggers and prepare histograms • Write log data and addr/count FIFOs 160 MHz 32 PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 160 MHz 32 32 SL 120 MHz ? 32 Either one or the other Inter-PP controller Input/output data FIFOs 32 32 L0 Primitive Merger[SD specific]output primitive FIFO • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 32 Bruno 32 32 160 MHz 160 MHz 160 MHz ? 16 16 PP

  9. 256 32 PP Franco ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 ? ECS • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests ALTERADDR controller = FIFO 32 Franco 32 40 MHz ? = 2012 32 ? = 2013 32 160 MHz • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 160 MHz 32 ? 32 32 32? 32 ? 32 ? 32 ? 160 MHz 32 32 • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO • Data Write Formatter • write data and addr/count FIFO • Split data in pages • Prepare error log pages • Write data and addr/count FIFOs 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) 32 • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors SL Marco 32 120 MHz ? 32 Franco 160 MHz 160 MHz • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 32 8 SL • Data monitor log data and addr/count FIFO • Monitor TDC data and errors and prepare histograms • Monitor L0 primitives and prepare histograms • Monitor received triggers and prepare histograms • Write log data and addr/count FIFOs 160 MHz 32 PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 160 MHz 32 32 SL 120 MHz ? 32 Either one or the other Inter-PP controller Input/output data FIFOs 32 32 L0 Primitive Merger[SD specific]output primitive FIFO • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 32 Bruno 32 32 160 MHz 160 MHz 160 MHz ? 16 16 PP

  10. Daughter card communication Data monitor • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors 32 • Data monitor log data and addr/count FIFO • Monitor TDC data and errors • and prepare histograms • Monitor L0 primitives • and prepare histograms • Monitor received triggers • and prepare histograms • Write log data and addr/count FIFOs 32 32 32 160 MHz 32 160 MHz Bruno

  11. 256 32 PP Franco ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 ? ECS • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests ALTERADDR controller = FIFO 32 Franco 32 40 MHz ? = 2012 32 ? = 2013 32 160 MHz • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 160 MHz 32 ? 32 32 32? 32 ? 32 ? 32 ? 160 MHz 32 32 • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO • Data Write Formatter • write data and addr/count FIFO • Split data in pages • Prepare error log pages • Write data and addr/count FIFOs 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) 32 • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors SL Marco 32 120 MHz ? 32 Franco 160 MHz 160 MHz • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 32 8 SL • Data monitor log data and addr/count FIFO • Monitor TDC data and errors and prepare histograms • Monitor L0 primitives and prepare histograms • Monitor received triggers and prepare histograms • Write log data and addr/count FIFOs 160 MHz 32 PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 160 MHz 32 32 SL 120 MHz ? 32 Either one or the other Inter-PP controller Input/output data FIFOs 32 32 L0 Primitive Merger[SD specific]output primitive FIFO • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 32 Bruno 32 32 160 MHz 160 MHz 160 MHz ? 16 16 PP

  12. DDR writing • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests 256 ALTERADDR controller ? ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 160 MHz 32 ? 32 32 40 MHz 32 ? Franco Franco 32 32 ? • Data Write Formatter • write data and addr/count FIFO • Split data in pages (25ns frames) • Prepare error log pages • Write data and addr/count FIFOs 32 160 MHz Franco

  13. 256 32 PP Franco ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 ? ECS • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests ALTERADDR controller = FIFO 32 Franco 32 40 MHz ? = 2012 32 ? = 2013 32 160 MHz • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 160 MHz 32 ? 32 32 32? 32 ? 32 ? 32 ? 160 MHz 32 32 • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO • Data Write Formatter • write data and addr/count FIFO • Split data in pages • Prepare error log pages • Write data and addr/count FIFOs 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) 32 • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors SL Marco 32 120 MHz ? 32 Franco 160 MHz 160 MHz • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 32 8 SL • Data monitor log data and addr/count FIFO • Monitor TDC data and errors and prepare histograms • Monitor L0 primitives and prepare histograms • Monitor received triggers and prepare histograms • Write log data and addr/count FIFOs 160 MHz 32 PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 160 MHz 32 32 SL 120 MHz ? 32 Either one or the other Inter-PP controller Input/output data FIFOs 32 32 L0 Primitive Merger[SD specific]output primitive FIFO • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 32 Bruno 32 32 160 MHz 160 MHz 160 MHz ? 16 16 PP

  14. Trigger handling and DDR reading • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 32 32 ? 160 MHz 32 32 32 32 ? 32 ? 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO SL Marco 120 MHz? • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 8 SL 160 MHz 160 MHz

  15. 256 32 PP Franco ECS DDR interface ECS write data FIFOECS RW addr/count FIFO 32 ? ECS • DDR arbiter • written addr/count FIFOSL read data and count FIFOECS read data and count FIFO • Handle ECS R/W requests and fill ECS read data and count FIFOs • Handle SL data read requests and fill SL read data and count FIFOs • Handle data write requests and fill written addr/count FIFO • Handle other write (and read ?) requests ALTERADDR controller = FIFO 32 Franco 32 40 MHz ? = 2012 32 ? = 2013 32 160 MHz • Data Read FormatterSL read data and count FIFO • Reject/compress data • Prepare event fragment frame 160 MHz 32 ? 32 32 32? 32 ? 32 ? 32 ? 160 MHz 32 32 • Data OrganizerSL read addr/count FIFO • Keep track of written words per page • Keep track of page expiration • Prepare SL read requests to DDR according to trigger info • Write read addr/count FIFO • Data Write Formatter • write data and addr/count FIFO • Split data in pages • Prepare error log pages • Write data and addr/count FIFOs 32 PP-SL data bus mux Communicate with SL(at 120 MHz ?) 32 • Input data Formatter4x (256x32) TDC input FIFOs3 copies of (256x32) output FIFO • Communicate with TDCs (at 40 MHz) • Merge TDC frames with same trigger timestamp • Check errors SL Marco 32 120 MHz ? 32 Franco 160 MHz 160 MHz • L0 Trigger Handler • Incoming trigger FIFO3 copies Read requests FIFO • Adjust timestamp (?) • Send read requests 32 8 SL • Data monitor log data and addr/count FIFO • Monitor TDC data and errors and prepare histograms • Monitor L0 primitives and prepare histograms • Monitor received triggers and prepare histograms • Write log data and addr/count FIFOs 160 MHz 32 PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 160 MHz 32 32 SL 120 MHz ? 32 Either one or the other Inter-PP controller Input/output data FIFOs 32 32 L0 Primitive Merger[SD specific]output primitive FIFO • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 32 Bruno 32 32 160 MHz 160 MHz 160 MHz ? 16 16 PP

  16. L0 primitive generation (SD specific) PP-SL trig bus mux Communicate with SL(at 120 MHz ?) 32 SL • L0 Primitive Generator[SD specific]primitive FIFO • Split data • Online corrections • Build primitives with fine time 120 MHz ? 32 Inter-PP controller Input/output data FIFOs Either one or the other 32 32 L0 Primitive Merger[SD specific]output primitive FIFO 32 32 ? 160 MHz 160 MHz 16 16 PP • May benotfullyimplementedfor 2012 runs. • Work started in Frascati (corrections) and Perugia (primitives). • Interactionswith Pisa groupneededto link thisblocksto the common part (redarrows) and to the coreservices, likeregisters and monitors.

  17. SL firmware 32 SL ECS QDR interface ECS • QDR arbiter • Handle ECS R/W requests • Handle MEP write requests • Handle MEP read requests • Handle other write (and read?) requests = FIFO 32 32 Elena 40 MHz = 2012 = 2013 160 MHz Elena • GbE controller • Handle data and trigger flows • Handle test data flows • Handle ARP 32 32 32 GbE 32 32 • Data Write Formatterwrite data FIFO • Prepare single events • Merge events into MEPs • Write data FIFO • Data Read Formatter • Read data from QDR • Prepare ethernet frames Marco 32 • PP data Formatter4x (256x32) PP FIFOs2 copies of output FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP data for same event 120 MHz 32 32 Marco 160 MHz 160 MHz PP 32 32 • TTC Handler • 2 copies of trigger FIFO • Set/store timestamp • Adjust timestamp (?) • Decode trigger word • Send triggers to PP • Data monitor log data FIFO • Monitor PP data and errors and prepare histograms • Monitor SL primitives and prepare histograms • Monitor received triggers and prepare histograms TTC 160 MHz 32 8 • L0 Primitive formatteroutput primitive FIFO • Prepare MTP • Prepare ethernet frames • Handle timeout • Handle LEMO triggers PP 32 160 MHz 40 MHz 32 • PP trigger primitive formatter[SD dependent]4x (256x32) PP FIFOs2 copies of output primitive FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP primitives 32 160 MHz 32 Inter-TEL62 controller Input/output data FIFOs L0 Primitive Merger[SD dependent]output primitive FIFO PP 32 32 32 Either one or the other 32 32 160 MHz 160 MHz ? 16 16 AUX

  18. 32 SL ECS QDR interface ECS • QDR arbiter • Handle ECS R/W requests • Handle MEP write requests • Handle MEP read requests • Handle other write (and read?) requests = FIFO 32 32 Elena 40 MHz = 2012 = 2013 160 MHz Elena • GbE controller • Handle data and trigger flows • Handle test data flows • Handle ARP 32 32 32 GbE 32 32 • Data Write Formatterwrite data FIFO • Prepare single events • Merge events into MEPs • Write data FIFO • Data Read Formatter • Read data from QDR • Prepare ethernet frames Marco 32 • PP data Formatter4x (256x32) PP FIFOs2 copies of output FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP data for same event 120 MHz 32 32 Marco 160 MHz 160 MHz PP 32 32 • TTC Handler • 2 copies of trigger FIFO • Set/store timestamp • Adjust timestamp (?) • Decode trigger word • Send triggers to PP • Data monitor log data FIFO • Monitor PP data and errors and prepare histograms • Monitor SL primitives and prepare histograms • Monitor received triggers and prepare histograms TTC 160 MHz 32 8 • L0 Primitive formatteroutput primitive FIFO • Prepare MTP • Prepare ethernet frames • Handle timeout • Handle LEMO triggers PP 32 160 MHz 40 MHz 32 • PP trigger primitive formatter[SD dependent]4x (256x32) PP FIFOs2 copies of output primitive FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP primitives 32 160 MHz 32 Inter-TEL62 controller Input/output data FIFOs L0 Primitive Merger[SD dependent]output primitive FIFO PP 32 32 32 Either one or the other 32 32 160 MHz 160 MHz ? 16 16 AUX

  19. SL data flow and TTC receiver 32 160 MHz • QDR arbiter Handle ECS R/W requests • Handle MEP write requests • Handle MEP read requests • Handle other write (and read?) requests ECS ECS QDR interface 32 32 40 MHz Elena Elena 32 32 32 • GbE controller • Handle data and trigger flows • Handle test data flows • Handle ARP • PP data Formatter4x (256x32) PP FIFOs2 copies of output FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP data for same event • Data Write Formatterwrite data FIFO • Prepare single events • Merge events into MEPs • Write data FIFO • Data Read Formatter • Read data from QDR • Prepare ethernet frames GbE 32 32 32 32 Marco 120 MHz 32 Marco PP 160 MHz 160 MHz 32 • TTC Handler • 2 copies of trigger FIFO • Set/store timestamp • Adjust timestamp (?) • Decode trigger word • Send triggers to PP 32 160 MHz • Data monitor log data FIFOMonitor PP data and errors and prepare histograms • Monitor SL primitives and prepare histograms • Monitor received triggers and prepare histograms TTC 8 32 PP 40 MHz 160 MHz

  20. 32 SL ECS QDR interface ECS • QDR arbiter • Handle ECS R/W requests • Handle MEP write requests • Handle MEP read requests • Handle other write (and read?) requests = FIFO 32 32 Elena 40 MHz = 2012 = 2013 160 MHz Elena • GbE controller • Handle data and trigger flows • Handle test data flows • Handle ARP 32 32 32 GbE 32 32 • Data Write Formatterwrite data FIFO • Prepare single events • Merge events into MEPs • Write data FIFO • Data Read Formatter • Read data from QDR • Prepare ethernet frames Marco 32 • PP data Formatter4x (256x32) PP FIFOs2 copies of output FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP data for same event 120 MHz 32 32 Marco 160 MHz 160 MHz PP 32 32 • TTC Handler • 2 copies of trigger FIFO • Set/store timestamp • Adjust timestamp (?) • Decode trigger word • Send triggers to PP • Data monitor log data FIFO • Monitor PP data and errors and prepare histograms • Monitor SL primitives and prepare histograms • Monitor received triggers and prepare histograms TTC 160 MHz 32 8 • L0 Primitive formatteroutput primitive FIFO • Prepare MTP • Prepare ethernet frames • Handle timeout • Handle LEMO triggers PP 32 160 MHz 40 MHz 32 • PP trigger primitive formatter[SD dependent]4x (256x32) PP FIFOs2 copies of output primitive FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP primitives 32 160 MHz 32 Inter-TEL62 controller Input/output data FIFOs L0 Primitive Merger[SD dependent]output primitive FIFO PP 32 32 32 Either one or the other 32 32 160 MHz 160 MHz ? 16 16 AUX

  21. Primitives merger and formatter 32 • L0 Primitive formatteroutput primitive FIFO • Prepare MTP • Prepare ethernet frames • Handle timeout • Handle LEMO triggers 32 • PP trigger primitive formatter[SD dependent]4x (256x32) PP FIFOs2 copies of output primitive FIFO • Communicate with PPs (at 120 MHz ?) • Check errors • Merge PP primitives L0 Primitive Merger[SD dependent]output primitive FIFO 32 160 MHz 32 Inter-TEL62 controller Input/output data FIFOs PP 32 32 32 Either one or the other 32 32 160 MHz ? 160 MHz 16 16 AUX

  22. Externalconnectionstests • Several blocks implemented to test external connections between FPGAs and other parts of TEL62: • Daughter-cards • DDR • PP-SL • Inter PP (not yet) • QDR • TTCrx • Gbit • Aux (not yet) • Used to test the TEL62 prototype in Pisa. • Possible use as partial test procedure for next board production while waiting for the final solution.

  23. FPGA resources PP SL 2% +60% DDR controller 2%

  24. Test benches in the FW

  25. Conclusions and future plans • The TEL62 firmware is on its way towards the dry run: • External connections testing blocks • Daughter-card communication • Data formatter and DDR interface • QDR interface • Data formatter and Gigabit controller • Sub-detectors data corrections and primitive generation • A still big amount of work is needed to complete the data-flow, from TDCs to Gbit and disk storage. • The trigger primitive generation, which mostly requires the involvment of SD people, should be instead completed during 2013.

More Related