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Firmware Overview and Status. Erno DAVID Wigner Research Center for Physics (HU). 26 January, 2016. CRU Block Diagram. CTP. FLP Server. CRU. Common CRU FW/SW Components provided by the CRU team. LTU. TTS. CRU Ctrl. Extensible by the Detector teams. RAM. Detector Data Frames. FEE.
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Firmware Overview and Status Erno DAVIDWigner Research Center for Physics (HU) 26 January, 2016
CRU Block Diagram CTP FLP Server CRU Common CRU FW/SW Components provided by the CRU team LTU TTS CRU Ctrl. Extensible by the Detector teams RAM Detector Data Frames FEE GBT PCIe User (detector specific) Logic Developed by the Detector and DCS teams Detector Control Frames Developed by the Detector and O2 teams FEE CPU FLP DAQ Software to EPN Servers NIC/IB GBTx, GBT-SCA FLP DCS Software to DCS Servers NIC
Different Communication Forms Between the CRU and the FEs Trigger and Timing CRU 40 MHz LHC Clock + 188 bit data (Orbit, BC, …) Data LTU SFP+ TTS CTP Busy DCS Busy FEE 40 MHz LHC Clock + 80 bit trigger (Orbit, BC, …) GBT LatOpt. Tx (24/36/48 link) 1 GBTx (ASIC) ASIC orFPGA 40 MHz LHC Clock 1 1 or 40 MHz x 80 bit DCS . . . Trigger or DCS(up to 40 e-links) 3 3 User (detector specific) Logic 3 GBT Tx DCS 4 40 MHz x 2 bit Internal SC I2C, SPI, GPIO, JTAG 40 MHz x 2 bit External SC 80 Mb/s 5 GBT-SCA(ASIC) . . . 5 2 PCIe, x16, Gen3, 128 Gbps GBT Rx GBT Std. Rx (24/36/48 link) 40 MHz x 80 bit FEE Data DATA 2 40 MHz x 2 bit Internal SC FEE Data (up to 40 e-links) . . . . . . 4 2 40 MHz x 2 bit External SC 5 4 5 DCS . . . • Main transactions: • Delivering the TTS information or Readout Control from CRU to FE • Receiving the detector data packets in serial and parallel form from the FE • Delivering custom packets from CRU to FE FPGA in parallel form • Sending and receiving packets to and from GBTx internal register block • Sending and receiving packets to and from GBT-SCA ASIC 1 2 3 4 5
GBT-Frame vs Different Communication Forms 120 bit @ 40 MHz 4 bit 2 bit 2 bit 80 bit 32 bit GBT Downlink (CRU -> FE) User Data Header IC EC FEC GBTx reg. access (e.g. TPC) GBT-SCA comm. GBT-SCA comm. (e.g. TPC) 80 bit TTS information (e.g. TOF) Detector specific readout control (e.g. TPC) Custom packet for FE FPGA (e.g. ITS) 120 bit @ 40 MHz 32 bit 4 bit 2 bit 2 bit 80 bit GBT Uplink (FE -> CRU) IC User Data Header EC FEC GBTx reg. access (e.g. TPC) GBT-SCA comm. GBT-SCA comm. (e.g. TPC) Multiple detector data packets in serial form (e.g. MCH) Single well formed CDH/SDH packet (e.g. TOF) Raw front-end data in Wide Bus Mode (e.g. TPC)
CRU Downstream Path (FLP -> FE) • 1. Common CRU Firmware • 80 bit trigger forwarding • Packet sender • 2. TPC, MCH, MID • FE readout-control 9.6 Gbps 10G PON TTS EMU 10G PON GBT Tx N x 80 bits @ 40 MHz User Logic Interconnect Can be upgraded for DMA Downlink 4.8 Gbps GBT GBT Payload Generator PCIe BAR Avalon-MM Master PCIe Endpoint 0 PCIe N x 2 bit N x 2 bit GBTx Packet Sender GBT-SCA Packet Sender
CRU Upstream Path (FE -> FLP) • 1. Common CRU Firmware • Packet receiver • 2. TPC • SAMPA raw data proc., CF • 3. MID • Custom serial packet decoder 9.6 Gbps 10G PON TTS EMU 10G PON GBT Rx N x 80 bits @ 40 MHz PCIe Endpoint 0, 1 User Logic PCIe DMA Uplink 0, 1 4.8 Gbps GBT Raw GBT Payload Recorder PCIe N x 2 bit N x 2 bit Interconnect GBTx Packet Receiver PCIe BAR Avalon-MM Master GBT-SCA Packet Receiver
Current CRU Firmware SoC Architecture cru_top_24.vhd tts_wrapper.vhd 10G PON QSYS design with 1 x 10G PON + Pattern Generator and Checker Avalon-MM Slave (xxx MHz, 32 bit) pcie_wrapper.vhd 40 MHz 184 bit 40 MHz 16 bit gbt_24_top.vhd QSYS PCIe Endpoint 0 user_logic.vhd 40 MHz, 24 x 80 bit 250 MHz 256 bit GBT 0 QSYSdesign with 24 x GBT + Pattern generator and Checker Avalon-ST Sink (250 MHz, 256 bit) User Logic Avalon-ST Source (xxx MHz, 256 bit) 40 MHz 24 x 4 bit PCIe 0 250 MHz 256 bit Avalon-MM Master Bridge(250 MHz, 32 bit) 40 MHz 24 x 80 bit Avalon-ST Source (xxx MHz, 256 bit) GBT 23 Avalon-MM Master Bridge(250 MHz, 32 bit) Avalon-MM Slave (xxx MHz, 32 bit) Avalon-MM Master Bridge(250 MHz, 32 bit) Avalon-MM Slave (xxx MHz, 32 bit) Avalon-MM Master Bridge(250 MHz, 32 bit) 40 MHz 24 x 4 bit dcs_wrapper.vhd QSYS PCIe Endpoint 1 GBTx GBT-SCA PCIe 1 Avalon-ST Sink (250 MHz, 256 bit) 250 MHz 32/64 bit Avalon-MM Slave (xxx MHz, 32 bit) 7
CRU Firmware Slow Control SoC Architecture FLP Server PCIe40 Board Linux CRU API Arria 10 FPGA O2 Software GBT-SCA User Logic TTS, GBT,…(core modules) [0..47] x 2 bit @ 40 MHz Custom Interface [0..47] x 2 bit @ 40 MHz QSYS PCIe Endpoint 0bar_x_masterAvalon-MM Master250 MHz x 32/64 bit DCS Software QSYS Interconnect (250 MHz x 32/64 bit) ??? Software GBTx ASIC I2C ? [0..47] x 2 bit @ 40 MHz [0..47] x 2 bit @ 40 MHz SFP+ Si 5338 MiniPOD 0 MiniPOD 7 Arria 10 Firmware Flash . . . 8
PCIe40 CRU Firmware Git Repository Status • Aim: • Provide the core features in a well separated way (everything is under /core directory) • The detector specific User Logic interacts with core features through a well defined interface • Heavy emphasis on command line scripting for easy integration with automated build system • Status: • Git repository: https://gitlab.cern.ch/alice-cru/pcie40cru • You can check out and build the core modules + TPC user logic placeholder git clone ssh://git@gitlab.cern.ch:7999/alice-cru/pcie40cru.git mkdir syn; cd syn quartus_sh --script ../pcie40cru/tpc/firmware/scripts/quartus/build.tcl -g ../pcie40cru • The missing features implemented as dummy logic to avoid dropping by optimization. • Ongoing development in the /core directory, but we should be able to work in parallel with the TPC and any other detector team through the User Logic Interface 9
Status of the Firmware Modules • TTS – the 10G PON downlink development just started, the emulator is developed by CTP • GBT – ongoing x24/x36/x48 development, the x6 design is tested with VLDB over single GBT links • PCIe – the two x8 endpoint is visible from Linux, the PCIe DMA controller (not yet started), PCIe Uplink packet aggregator (not yet started) • GBTx – not yet started • GBT-SCA – a basic SCA IP (with polling) is in the early phase of development • CRU Control – not yet started • Raw GBT Payload Recorder – not yet started • Packet Based Communication for Common CRU Firmware – not yet started • Data Generator – not yet started • Multiplexers, Demultiplexers, Proxies, Arbitrators - not yet started 10
