GCT Main Crate Status Hardware & Firmware
70 likes | 204 Vues
This report outlines the current status of hardware and firmware developments related to GCT systems, as managed by Greg Iles. Key highlights include thorough testing of 16 Leaf cards, 3 concentrator cards pending software completion, and 12 OGTI boards ready for PCB production. The firmware is stable, and ongoing tasks aim to optimize performance and manage latencies. Safety improvements for power supply connections are also slated for implementation. Overall, we are on track for further progress pending assembly quotes and software refinements.
GCT Main Crate Status Hardware & Firmware
E N D
Presentation Transcript
GCT Main Crate StatusHardware & Firmware GCT Status: Greg Iles
Hardware • Tested hardware • 16 Leaf cards • Fully tested • 3 Concentrator cards • Except Slink path (awaiting software) • 3 Wheel cards • Some may need JTAG fix • Further 2 recently received from ElFab • 2 GTI (Getty) cards • Fully tested • 12 OGTI (Oogetty) cards • Artwork/Netlist to be sent to ElFab today • All major parts in hand • Will make 12 PCBs (cost the same for 2) • Need to get quote for assembly from Exception • Will use if not too expensive • Will request that GT group considfer moving GTLP signals onto motherboard • no change to OGTI GCT Status: Greg Iles
Firmware • Firmware stable: • No new suprises when design resynthesised • Tweaking firmware • To do list: • Understand discrepancy between Data and BC0 observed at Concentrator • Add TotalEt, MissEt, TotalHt • Add status info to slink packet • e.g. number of operating links • Latency reduction • Change DDR regs between Wheel/Conc (1bx) • Reduce processing time in Wheel (1bx) • OGTI • Firmware being asembled (see separate slide) GCT Status: Greg Iles
USC55 • Refurbish USC55 System • Swap Wheel for one with JTAG fix • Bolt Leaf Sharing Samtec Cables (one wheel) • Increase clearance on front panels • Improve safety of power supply • Protect power bin connectors • Crate power bin connectors are deep inside the rack • If you were very determined you might be able to short connectors out with something like a screwdriver • Highly unlikely scenario, but ought to protect power bin connectors • Not completely trivial because cannot use original power bin cover • Double insulate the ends of power cables. Single layer of heavy duty heatshrink between GND/+5V on power bin at present. • Just make this more robust. • Main Crate JTAG • Was to be done via VME • Xilinx ISE now allows you to program multiple FPGAs in one go. • Perhaps we should just use this? • Can save load config GCT Status: Greg Iles
OGTI-Tx • Tx firmware • Unable to find ‘nice’ way to extend source card timing constraints to a large system • No nice way of tagging requirement in VHDL • Oversample incoming 80MHz data at up to 400MHz. • Choose optimum sampling point, if it exists, for each 100MHz clock • Advantages: • Bridges into 100MHz domain in < ½ bx • Automatically adjusts for phase of 80MHz data • No constraints in UCF • Disadvantage: • Need to run input clks quite quick • Not that generic • 2.4Gb/s link or 3.2Gb/s link would require slight tweak to firmware • Requires data valid type signal from conc card. • Assumes input data aligned to better than 1ns GCT Status: Greg Iles
OGTI-Rx • Rx firmware • Want links to automatically align • Will not try to “reinvent wheel” • Use existing code from John or Magnus • Magnus’ code • Will probably be backwards compatible with current software • May split link config into setup/auto-align • find optimum latency position in receive fifo using software • then relatively trivial to have each link auto-align in firmware • Still being written…. • John’s code • All sorts of clever ideas ! • E.g. use of k-codes (albeit with small latency hit) • Perhaps more R&D • Also still being written… ? GCT Status: Greg Iles
End GCT Status: Greg Iles
