1 / 2

Status Update on XTC Firmware Development and Testing as of September 15, 2004

As of September 15, 2004, we have compiled a firmware project using Quartus 4.1 that functions in VME32 mode across both prototype and new boards. It features a new VME64 data bus in High Z mode, though it currently lacks LVDS_tx implementation. The edge detector can manage up to 5 hits per channel, and CBLT32 transfers have been tested. However, the edge detector needs enhancement for up to 7 hits. Upcoming work includes debugging XFT issues and implementing a simple counter for XFT outputs to facilitate PCB connectivity testing.

beverly-bishop
Télécharger la présentation

Status Update on XTC Firmware Development and Testing as of September 15, 2004

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. XTC Firmware status TDC Firmware Status as of 9/15/04: We have a firmware project compiled 9/10/04 with Quartus 4.1 that can work in VME32 mode on both our prototype boards and the new boards: - It has a new VME64_data[31..0] bus included, but set in High Z; - No LVDS_tx implementation. Tested: - Edge Detector works for up to 5 hits per channel; - CBLT32 transfers tested. Limitations:- ED needs to work for up to 7 hits and Mary is working on that right now; - XFT has some problems and Sasha will work on that next week. We can use this firmware as is to test the new boards: ED and CBLT32.

  2. XTC Firmware status • XFT Testing Options: • If we debug XFT Block Design Changes next week => O.K. • If not => implement simple counter inside chip to generate pulses on the XFT outputs => testing PCB connectivity to P3. • CBLT64 Testing: • More involved, more changes on the "main_chip" and "tdc_vme_chip" firmware designs.

More Related