TDCB status and Firmware updates

1. TDCB status and Firmware updates Andrea Burato (INFN Pisa) On behalf of TDCB working group TDAQ working group meeting 24.03.2010

2. Summary / Outline • Status of the TDC Board • TDCB firmware funtionalities and features • Firmware updates: • TDC / FPGA comunication • Periodic-trigger mode • Registers manual

3. Status of TDC Board Brief reminder: • New FPGA Cyclone III and new PCB with some correction and improvement • Layout made at CERN on December ‘09 • 20 PCB produced and 2 board assembled for testing Cost 956 € all included Worst case including T.V.A. (not present in production) and with orders of very small componentsvolume for prototypes After testing some other boards can be assembled. Ask now!!

4. Status of TDC Board Cables for preliminary TDCB V3 testing: Two amphenol cables • skewclear • 34 couples • high performance • halogen free Cost 230 € (prototype) Not final solution too good and too expensive • Started market survey: twisted-pair cable + VHDCI connector • Investigation for a home-made solution (Pisa)

5. TDCB firmware In previous test TDCB-FPGA were not used and TDCs spoke directly to TELL1 through FPGA, now it changes TDCB Firmware Main features: • TDC / FPGA interface • jtag TDC configuration settings • data transfer from TDC to FPGA • TDCB-FPGA / TELL1 (PP-FPGA) interface • I2C comunication for slow control • data transfer from FPGA to TELL1 • Trigger functionality

6. TDCB firmware TDC / FPGA interface • TDC configuration via jtag • Data transfer from TDC buffer into FPGA internal FIFO (new feature)

7. TDCB firmware TDCB-FPGA / TELL1 (PP-FPGA) interface • I2C comunication to write an read TDCB-FPGA registers • data transfer from FPGA internal FIFOs to PP FIFOs (new feature) • TDCB: • One FIFO of 32x256 words for each TDC • One read-out buffer for each FIFO PP sees the FIFO like a TDC PP-firmware remains the same

8. TDCB firmware Complete read-out scheme: • Possibility to make pre-processing using RAM equipped on TDCB • Possibility to inject data for testing • Monitoring

9. TDCB firmware Trigger functionality Before: TDC continuously reading (triggerless mode) Now: TDC used in trigger mode with a periodic trigger from FPGA • TDC sends data belonging to a changeable time window • Each TDC red independently on a different bus (40 Mhz) but same trigger

10. Firmware Updates Periodic-trigger mode TDC side • A periodic trigger is sent from the FPGA to TDC Ttrg range: 0.4 - 38.4 µs with step of 0.4 µs • TDC load in readout buffer all data that match a specific time window • Each data packet, send to FPGA, concerns a trigger • In periodic trigger mode the time window is equal to trigger period All data are sending to FPGA

11. Firmware Updates Periodic-trigger mode FPGA side • Adds Time Stamp (TS) at the beginning of data packet from TDC TS ID: Time Stamp identification code Course count: LSB 0.4 µs range from 0.4 µs to100 s • Transfers data into internal FPGA FIFO (one for each TDC) • Adds to data packet a final word with words count

12. Conclusions • 20 PCB ready • 2 board assembled and ready for test • 2 Amphenol prototype cables • New firmware feature: periodic trigger mode To do list: • Test new card • Measure clock jitter / time resolution • Test again TDC rate limits • Firmware improvements After testing some other boards can be assembled. Ask now!!

13. Spare