Digital Design and Synthesis with Verilog HDL

1. DigitalDesignandSynthesiswithVerilog HDL Eli Sternheim, Ph.D. interHDL, Inc. Rajvir Singh interHDL, Inc. Rajeev Madhavan Cadence Design System,Inc. Yatin Trivedi YT Associates

2. Chapter 1 • Why hardwaredescriptionlanguages? • Evolutionary trends in design methods. • The use of hardware description languages (HDLs) for logic design has greatly expanded in the last few years. • Engineering managers no longer face the dilemma of whether to design with an HDL or not.

3. Designing with Verilog HDL • Verilog HDL is simple and elegant. • It provides constructs to describe hardware elements in a succinet and readable form. • A comparable description, for example in VHDL, can be twice as long as a Verilog description.

4. Designing with Verilog HDL • In Verilog, a designer needs to learn only one language for all aspects of logic design. • Simulation of a design, at least, requires functional models, hierarchical structures, test vectors, and man/machine interaction. • In Verilog, all of these are achieved by one language. • Almost every statement that can be written in procedural code can also be issued in an interactive session from the terminal.

5. Designing with Verilog HDL • Verilogis not only concise and uniform, but also is easyto learn. • It is very similar to the C programming language. • Since C is one of the most widely used programming languages, most designers should be familiar with it and may, therefore, find it easy to learn Verilog.

6. Chapter 2 • Anatomy of the Verilog HDL • In this chapter we introduce the Verilog hardware description language through a sequence of examples. • A more complete specification of the language can be found in the ”Language Reference Manual” and in the ”Condensed Reference Manual” in Appendix A.

7. Anatomy of the Verilog HDL • A module definition example, structural style. //structural module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2, out; and u1 (out, in1, in2); endmodule

8. //data flow module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2, out; assign out = in1 & in2; endmodule Anatomy of the Verilog HDL • A module definition example, data flow style.

9. Anatomy of the Verilog HDL • A module definition example, behavioral style //behavioral module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2; reg out; always @ (in1 or in2) out= in1 & in2; endmodule

10. Anatomy of the Verilog HDL • Test Fixture for and2 module module test_and2; reg i1, i2; wire o; AND2 u2 (i1,i2,o); initial begin i1=0; i2=0; #1 $display (”i1=%b, i2=%b, o=%b”, i1, i2, o ); i1=0; i2=1; #1 $display (”i1=%b, i2=%b, o=%b”, i1, i2, o ); i1=1; i2=0; #1 $display (”i1=%b, i2=%b, o=%b”, i1, i2, o ); i1=1; i2=1; #1 $display (”i1=%b, i2=%b, o=%b”, i1, i2, o ); end endmodule • Test results i1=0, i2=0, o=0 i1=0, i2=1, o=0 i1=1, i2=0, o=0 i1=1, i2=1, o=1

11. Anatomy of the Verilog HDL • Structural and_or module example. module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; wire tmp and #10 u1 (tmp, in1, in2 ) , u2 (undec, in3, in4 ); or #20 (out, tmp, undec ); endmodule • Data flow and_or example. module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; wire tmp; assign #10 tmp= in1 & in2; wire #10 tmp1= in3 & in4; assign #20 out= tmp | tmp1; // The three assignments could be condensed //into one: //assign #30 out=(in1 & in2) | (in3 &in4); endmodule

12. Anatomy of the Verilog HDL • Behavioral and_or example. module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; reg out; always @ (in1 or in2 or in3 or in4) begin if (in1 & in2 ) out = #30 1; else out = #30 (in3 & in4); end endmodule

13. Anatomy of the Verilog HDL • Test fixture for and_or module. And_or simulation results

14. Anatomy of the Verilog HDL • Basic Operators and Expressions integer i, j ; //two integers real f, d; //two real numbers wire [7:0] bus; //8-bits wide bus reg [0:15] word; //16-bits wide word reg arr [0:15]; //array of 16 one-bit reg`s reg [7:0] mem[0:127]; //array of 128 bytes event trigger, clock_high; //two events time t_setup, t_hold; //t1, t2 parameter width= 8; parameter width2= width*2; wire [width-1:0] ww; //the following are illegal: wire w[0:15]; //wires cannot be in arrays wire [3:0] a, [7:0]b; //only one width specification per declaration

15. Anatomy of the Verilog HDL • Summary of Verilog Operators Operator Precedence

16. Anatomy of the Verilog HDL • Difference between = = and = = =

17. Anatomy of the Verilog HDL • Concatenation and replication

18. Anatomy of the Verilog HDL • A for statement Results of for_loop execution

19. Anatomy of the Verilog HDL A case statement • A while_loop statement

20. Anatomy of the Verilog HDL • A repeat loop A forever loop

21. Anatomy of the Verilog HDL • The axis of time current time t1 t2 t3 Multiple behavioral instances

22. Anatomy of the Verilog HDL #expression @event-expression wait (expression) Example of time control

23. Anatomy of the Verilog HDL • Example of event control

24. Anatomy of the Verilog HDL • Example of parallel processes Example of disable

25. Anatomy of the Verilog HDL • Simulating break and continue statements Example of a task

26. Anatomy of the Verilog HDL • Example of a function

27. Anatomy of the Verilog HDL • Behavioral description of a 4-bit adder

28. Anatomy of the Verilog HDL • Using an initial forever assignments

29. Anatomy of the Verilog HDL • Using a continuous assignment

30. Anatomy of the Verilog HDL • Structural description of 4-bit adder Behavior of a 1-bit full adder

31. Anatomy of the Verilog HDL • Mixed mode representation

32. Chapter 3 • Modeling a Pipelined Processor • In this chapter we take the specification of a 32-bit processor and develop a functional model for it through various stages of successive refinement. • First we implement an instruction set model, then we describe a register transfer level (RTL) model. • In the next chapter we arrive at a structural model that maps the processor to various building blocks. • In the process, we explain modeling of such concepts as pipelining, concurrency, instruction execution, functional partitioning, and creation of test vectors.

33. Modeling a Pipelined Processor • The emphasis here is on the process of modeling as opposed to describing the architecture of a processor. • It is not our intention to explain the detailed functionality of any commercial microprocessor or architecture. • Some discussion on processor architecture is presented to explain the concepts and process of modeling.

34. Chapter 4 • Modeling System Blocks • In the previous chapter we saw how to model a processor at the instruction set level and its function at the behavioral level. • In this chapter we present a structural model of the SISC processor and show how to model its various building blocks. • We begin with the block diagram of the SISC processor and present its corresponding structural model to show the interconnections of its building blocks. • In subsequent sections we develop functional models for these blocks, namely, the datapath, the memory elements, the clock generator and the control unit.

35. Chapter 5 • Modeling Cache Memories • In this chapter we examine the process of designing a simple cache system in Verilog HDL. • The description can be synthesized to obtain a gate level implementation. • At the end of this chapter we consider ways to improve the basic design.

36. Modeling Cache Memories • A cache in a computer system is a small, fast, local memory that stores data from the most frequently accessed addresses. • The cache is always small compared to main memory because cache RAMs are more expensive then the slower dynamic RAMs used for main memory. • As a result, only a small portion of the main memory can be stored in the cache. • The efficiency of a cache is measured by the cache hit ratio, i.e., the number of times data is accessed from the cache over the total number of memory accesses. • Typical hit ratios are in the range of eighty to one hundred percent.

37. Chapter 6 • Modeling Asynchronous I/O: UART • In this chapter we present an example of modeling an asynchronous peripheral device, a dual Universal Asynchronous Receiver Transmitter (UART) chip. • We develop two models of the chip. • The first model is a high-level abstractionwhich describes the functionality of the chip and emphasizes simplicity, readability and ease of change. • The second model is oriented toward gate-level implementation. • This model is partitioned so that a logic synthesizer can be used to automatically implement the chip with library components.

38. Chapter 7 • Verilog HDL for Synthesis • In the previous chapters we introduced Verilog HDL and showed how it can be used in different ways to support top-down hierarchical design. • In this chapter we cover the basics of synthesis, discuss how Verilog may be used for synthesis and describe how modeling for synthesis affects the coding style, the design organization and partitioning.

39. Chapter 8 • Modeling a Floppy Disk Subsystem • In this chapter we provide a complete example of a floppy disk subsystem (FDS) model in Verilog. • Such a model may be needed when you perform a full system simulation and want to simulate the execution of code which accesses the disk. • The FDS model would typically be used to perform a full functional simulation during the development of a CPU board. • This example demonstrates the modeling of asynchronous systems, I/O buses, timing constraints, and other techniques of writing large models.

40. Chapter 9 • Useful Modeling and Debugging Techniques • Learning to design and simulate in Verilog is more then just learning the syntax and semantics of the language. • As in every learning process, the best way to learn is by doing. • As you start using the language, you will develop your own style of design, and you will discover techniques for modeling in Verilog. • In this chapter we present some tips and techniques that we hope will help you in developing your own techniques on the way to mastering Verilog.