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The Case for MyHDL

The Case for MyHDL. Wesley New SKA-SA wesley@ska.ac.za. MyHDL Introduction. Provides a High-level Hardware description and verification language for Modeling of Hardware Based on Python Enables easy simulation Open-source. How does MyHDL Model Hardware in a Functional/O-O Language.

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The Case for MyHDL

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  1. The Case for MyHDL • Wesley New • SKA-SA • wesley@ska.ac.za

  2. MyHDL Introduction • Provides a High-level Hardware description and verification language for Modeling of Hardware • Based on Python • Enables easy simulation • Open-source

  3. How does MyHDL Model Hardware in a Functional/O-O Language • Concurrency • A = 1 • B = A • Generators provide an elegant solution for modeling concurrency • A generator is a resumable function • Instead of return we use yield

  4. Generators def function(): for i in range(5): return i Function is terminated on the return function() 0 function() 0

  5. Generators def generator(): for i in range(5): yield i g = generator() g.next() 0 g.next() 1 g.next() 2 . .

  6. MyHDL and Simulation • Very easy to simulate designs • Incorporate the functionality of packages such as numpy and scipy • VCD file to view with gtkwave

  7. HDL Generation • MyHLD provides 2 functions to convert to HDL • toVerilog() • toVHDL() • Converts the method passed to it and all methods called within.

  8. Matlab and Simulink • Low barrier to entry due to simplistic block diagram interface • Matlab often Hangs/Crashes when redrawing or compiling larger designs • Hassle to simulate • Support • Licensing Fees for Non-Profits

  9. Current Toolflow Design • Matlab/Simulink • Design • Simulation • Output • S/W Application & Simulation • Application design using • Yellow Blocks, IP Cores and • Primitives. • Simulation in simulink • Primatives • IP Cores • System Generator • SG pulls together all the primitives, yellow blocks. • IP is generated • System Generator • Yellow Blocks • Project Generation Scripts • Generate Xilinx project • Incorporate base project • Generate mhs file • Base Project • MHS • ISE/EDK Project • Compile Project • Synthesis • Place and Route • Map • Creates bit file • Bitstream • Coreinfo • BOF File • Generate BOF File • Gen memory interface description • Gen ELF header

  10. Matlab/Simulink • Desin • Simulation • Output • S/W Application & Simulation • Application design using • Yellow Blocks, IP Cores and • Primitives. • Simulation in simulink • Primatives • IP Cores • System Generator • SG pulls together all the primitives, yellow blocks. • IP is generated • System Generator • Yellow Blocks • Project Generation Scripts • Generate Xilinx project • Incorporate base project • Generate mhs file • Base Project • MHS • ISE/EDK Project • Compile Project • Synthesis • Place and Route • Map • Creates bit file • Bitstream • Coreinfo • BOF File • Generate BOF File • Gen memory interface description • Gen ELF header

  11. MyHDL Toolflow Design • Design • Simulation • Output • Simulation Logic • S/W Application & Simulation • Application design using • MyHDLmodules, IP Cores and • HDL modules. • Simulation in Python • Configuration/Settings • Project Initialisation • Initiate Base Design • Design Rules Check • Generate HDL from MyHDL • Generate IP with CoreGen • MyHDL • HDL Cores • CoreGen • Project Integration • Generate Top Level HDL file • Bus Management • Incorporate UCF file • Toplevel HDL • UCF • UCF • Compile Project • Synthesis • Place and Route • Map • Creates bit file • Bitstream • Coreinfo • BOF File • Generate BOF File • Gen memory interface description • Gen ELF header

  12. Design • Simulation • Output • Simulation Logic • S/W Application & Simulation • Application design using • MyHDLmodules, IP Cores and • HDL modules. • Simulation in Python • Configuration/Settings • Project Initialisation • Initiate Base Design • Design Rules Check • Generate HDL from MyHDL • Generate IP with CoreGen • MyHDL • HDL Cores • CoreGen • Project Integration • Generate Top Level HDL file • Bus Management • Incorporate UCF file • Toplevel HDL • UCF • UCF • Compile Project • Synthesis • Place and Route • Map • Creates bit file • Bitstream • Coreinfo • BOF File • Generate BOF File • Gen memory interface description • Gen ELF header

  13. Integrating MyHDL with the CASPER toolflow • Libraries, IPcores • Wrapping HDL Modules • Base Design • Bus Management • Simulation of wrapper blocks • Support our own tool flow

  14. Challenges • Generated HDL is a flat file, very hard to debug • Implementing the functionality of System Generator • Bus management • Floating point arithmetic unsupported • Can we trust the generated HDL • On-the-fly generation of IPcores

  15. Future Development • One click compile • Vendor Agnostic (Xilinx, Altera) • GUI for block diagram design

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