VHDL Designs for Digital Circuits Implementation
Learn about VHDL entities, architectures, and components for designing digital circuits. See examples of gate networks, memories, and hierarchical designs.
VHDL Designs for Digital Circuits Implementation
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LIBRARYIEEE; -- Include Libraries for standard logic data types USEIEEE.STD_LOGIC_1164.ALL; -- Entity name normally the same as file name ENTITY gate_network IS -- Ports: Declares module inputs and outputs PORT( A, B, C : INSTD_LOGIC; -- Standard Logic Vector ( Array of 4 Bits ) D : INSTD_LOGIC_VECTOR( 3 DOWNTO 0 ); -- Output Signals X, Y : OUTSTD_LOGIC ); END gate_network; -- Defines internal module architecture ARCHITECTURE behavior OF gate_network IS BEGIN -- Concurrent assignment statements operate in parallel -- D(1) selects bit 1 of standard logic vector D X <= A ANDNOT( B OR C ) AND ( D( 1 ) XOR D( 2 ) ); -- Process must declare a sensitivity list, -- In this case it is ( A, B, C, D ) -- List includes all signals that can change the outputs PROCESS ( A, B, C, D ) BEGIN -- Statements inside process execute sequentially Y <= A ANDNOT( B OR C) AND ( D( 1) XOR D( 2 ) ); ENDPROCESS; END behavior;
LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; LIBRARYAltera_mf; USEaltera_mf.altera_mf_components.all; ENTITY amemory IS PORT( read_data : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); memory_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); write_data : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); Memwrite : IN STD_LOGIC; clock,reset : IN STD_LOGIC ); END amemory; ARCHITECTURE behavior OF amemory IS BEGIN data_memory: altsyncram -- Altsyncram memory function GENERICMAP ( operation_mode => “SINGLE_PORT”, width_a => 8, widthad_a => 3, lpm_type => “altsyncram”, outdata_reg_a => "UNREGISTERED", -- Reads in mif file for initial data values (optional) init_file => "memory.mif", intended_device_family => “Cyclone” ) PORTMAP (wren_a => Memwrite, clock0 => clock, address_a => memory_address( 2 DOWNTO 0 ), data_a => write_data, q_a => read_data ); END behavior;
ENTITY hierarch ISPORT ( clock_25Mhz, pb1 : INSTD_LOGIC; pb1_single_pulse : OUTSTD_LOGIC);END hierarch;ARCHITECTURE structural OF hierarch IS-- Declare internal signals needed to connect submodulesSIGNAL clock_1MHz, clock_100Hz, pb1_debounced : STD_LOGIC;COMPONENT debounce -- Use Components to Define Submodules and ParametersPORT( pb, clock_100Hz : INSTD_LOGIC; pb_debounced : OUTSTD_LOGIC);ENDCOMPONENT; COMPONENT onepulsePORT(pb_debounced, clock : INSTD_LOGIC; pb_single_pulse : OUTSTD_LOGIC);ENDCOMPONENT;COMPONENT clk_divPORT( clock_25Mhz : INSTD_LOGIC; clock_1MHz : OUTSTD_LOGIC; clock_100KHz : OUTSTD_LOGIC; clock_10KHz : OUTSTD_LOGIC; clock_1KHz : OUTSTD_LOGIC; clock_100Hz : OUTSTD_LOGIC; clock_10Hz : OUTSTD_LOGIC; clock_1Hz : OUTSTD_LOGIC);ENDCOMPONENT; BEGIN-- Use Port Map to connect signals between components in the hierarchydebounce1 : debounce PORTMAP ( pb => pb1, clock_100Hz = >clock_100Hz, pb_debounced = >pb1_debounced);prescalar : clk_div PORTMAP ( clock_25Mhz = >clock_25Mhz, clock_1MHz =>clock_1Mhz, clock_100hz = >clock_100hz);single_pulse : onepulse PORTMAP ( pb_debounced = >pb1_debounced, clock => clock_1MHz, pb_single_pulse => pb1_single_pulse);END structural;
