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Advanced RPC VME Hardware Setup and Control with Embedded PC and JTAG Utilities

This comprehensive package includes tools for configuring and operating the RPC VME hardware equipped with an embedded PC running EtLinux. Key applications feature utilities for loading Altera FPGAs, JTAG operations, and control of TTCvi/TTCrx boards. It provides a simple command line interface, an intuitive GUI for hardware control, and high-performance applications like TBCC for beam tests. Users can manage sequences, presets, and efficient readouts with libraries for histogramming, testing, and generating signals. Ideal for both experts and non-experts alike.

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Advanced RPC VME Hardware Setup and Control with Embedded PC and JTAG Utilities

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  1. RPC Trigger Software

  2. VME Hardware setup TB equipped with embedded PC (EtLinux) RPC VME-PCI SBS Interface Bit3 Controller Trigger Board Pattern Unit TTCvi Link Board 1 Link Board 2 Link Board 3 Link Board 4 WinNT 4 PCI-VME Ethernet Michał Pietrusiński

  3. Applications • aboot – command line utility to load Altera FPGAs • interbs – simple command line utility to interact with JTAG boards • Basic JTAG operations (TAP state, send/receive vectors of bits) • Chip and board level operations – access to elements by its name: • read/write specific chip registers • execute JTAG instructions • set/get state of specific pin/signal Michał Pietrusiński

  4. interbs – example of usage suncms1:/usr/local/bin>interbs chain.bsc PAC:pt ALTERA:ap PAC:pac ALTERA:ac interbs>reset interbs>ss pt BYPASS interbs>ss ap BYPASS interbs>ss pac SAMPLE interbs>ss ac BYPASS interbs>sir sending sequence:11101001111111 received=10110001011000 interbs>sdr sending sequence: 00000000000000000000000000000000000000000000000000000000000000000000000 Received sequence: 00000000000000000000000000000000000000000000000000000000000000000101000 interbs>gs pac|BOUN_REG|sig|codeout3 o1 interbs>gs pac|BOUN_REG|sig|codeout4 o0 interbs>gs pac|BOUN_REG|sig|codeout5 o1 interbs>gs pac|BOUN_REG|sig|codeout6 o0 interbs>quit List of chips in the chain Set TAP to Reset state Prepare the program to execute given instructions in chips Send/rec sequence to instruction registers Send/rec sequence to data registers (length of chain is calcuated automaticaly) Print state of some signals: o1 - output high o0 – output low Michał Pietrusiński

  5. Applications (cont’d) • TTCcontr – Windows application that gives full control of TTCvi andTTCrx boards • Supports older (TTCvi MK I) and latest (TTCvi MK II) versions of TTCvi • Easy control of all TTCvi and TTCrx functions and settings • User-defined sequences of B-Channel cycles stored in ini file • Presettings (stored in ini file) - user can save current settings of TTCvi and TTCrx and apply theme later byclicking one button Michał Pietrusiński

  6. TTC screenshot Michał Pietrusiński

  7. Applications (cont’d) • punit – visual Windows application to send test pulses using Pattern Unit (one word = 128 bits) • edit scripts wtih signal definitions, macros, loops, etc. • parse, programm device, run. • tbcc (Test Bench Control Center) – visual application used to control RPC trigger prototypes during beam tests. • Setting control registers. • Histogramming Michał Pietrusiński

  8. Beam-test software goals • Hardware setup and control (FPGAs loading, setting control registers) • Readout of boards, histogramming • Intuitive GUI: software is to be used by non software experts • Reusable, easy to modify • High performance Michał Pietrusiński

  9. Tbcc screenshot Michał Pietrusiński

  10. Packages • VME library • Altera loading package • JTAG primitives library (bscontr) • JTAG layout library (bslayout) • Test pulses generation library (punit) • Histogramming package • Internal Interface (II) package • TTCvi package Michał Pietrusiński

  11. Package dependencies Michał Pietrusiński

  12. Boundary Scan package Michał Pietrusiński

  13. Internal Interface package Michał Pietrusiński

  14. II: VHDL and C++ • VHDL and C++ code use common interface description files (iid) • IID files describe: • Registers, meanings of bits in registers, memory areas • Their sizes • Types of access • IID files are directly included in C++ projects and automatically converted to VHDL using C++ preprocessor. Michał Pietrusiński

  15. Tbcc screenshot II From lb_control.iid: IIDEC_COM_LINE( " item type item ID width num parent ID IIDEC_ITEM_BEG( VII_PAGE, PAGE_REGISTERS, 0, 0, PAGE_REGISTERS, ... IIDEC_ITEM_CON( VII_WORD, WORD_IDENTIFIER, II_DATA_SIZE, 1, PAGE_REGISTERS, ... IIDEC_ITEM_CON( VII_WORD, WORD_VERSION, II_DATA_SIZE, 1, PAGE_REGISTERS, ... IIDEC_ITEM_CON( VII_VECT, VECT_STATUS, 0, 0, PAGE_REGISTERS, ... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_CLOCK_SEL, CLOCK_SEL_SIZE, 1, VECT_STATUS, ... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_TRG_SEL, TRG_SEL_SIZE, 1, VECT_STATUS, ... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_PRETRG0_SEL, PRETRG_SEL_SIZE, 1, VECT_STATUS, ... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_PRETRG1_SEL, PRETRG_SEL_SIZE, 1, VECT_STATUS, ... IIDEC_ITEM_CON( VII_VECT, VECT_GOL, 0, 0, PAGE_REGISTERS, ... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_LASER, 1, 1, VECT_GOL, ... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_NEDGE, 1, 1, VECT_GOL, ... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_TX_ENA, 1, 1, VECT_GOL, ... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_TX_ERR, 1, 1, VECT_GOL, ... Michał Pietrusiński

  16. Histogramming package Michał Pietrusiński

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