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Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development

M. Noy 29-01-2003. Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development Summary. Some known (and relevant) signal. Data processing. FF1 emulator (SW). FF1 (real). SW comparison of processed data. Analysis of functionality

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Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development

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  1. M. Noy 29-01-2003 • Final FED 1 Testing Set Up • Testing idea and current status • Preliminary results • Future development • Summary

  2. Some known (and relevant) signal Data processing FF1 emulator (SW) FF1 (real) SW comparison of processed data Analysis of functionality (later  pass/fail) Software Control M. Noy 29-01-2003 Testing idea

  3. System status M. Noy 29-01-2003

  4. DAC Vocm M. Noy 29-01-2003 VME interface for PC control 010 12 bit DAC and fully differential op-amp with common mode offset analogue opto-tx digital sequencer 40MHz

  5. M. Noy 29-01-2003 Sequence control logic Sequence storage  Analogue section  VME interface logic DAC Amplification+cm Analogue opto-tx

  6. M. Noy 29-01-2003 Software I have developed software using XDAQ and the HAL FedTesterObject: encapsulates functionality  interface FedTesterApplication: instantiates a (the) FedTesterObject(s); inherits from xdaqApplication and FedTesterSOAPCommandListener Plus additional required SO class

  7. M. Noy 29-01-2003 Results from the system: preliminary

  8. M. Noy 29-01-2003 The optical output is fed into the first Optobahn opto-rx version, through 50 co-ax, into a 50 terminated scope. Analogue square wave, period 50ns. (channel 0, bias setting 0x17, gain setting 1) 10% to 90% rise time: 3.60.2 ns 90% to 10% fall time: 3.40.2 ns Settling time believed to be better than 17ns, analogue noise believed to be less than 10mV, but not characterised yet.

  9. M. Noy 29-01-2003 Linearity looks sufficient, but no detailed measurements have been made yet.

  10. M. Noy 29-01-2003 Muxed pair of APV25 frames with pedestals only. ticks pedestals Error bits Header

  11. M. Noy 29-01-2003 Muxed pair of APV25 frames with a 1 MIP (approx.) hit

  12. M. Noy 29-01-2003 HIP event: from the X5 beam test data. R. Bainbridge, M. Takahashi

  13. M. Noy 29-01-2003 Development

  14. 4x6U VME cards Acting master VME Master trigger in Clock and trigger distribution (propagation matched lines) M. Noy 29-01-2003 4 identical VME boards 6U in size

  15. VME Master triggers in Front End Modules BE to FE bus with clock and L1A BE V2 Slave trigger and clock Temp unit M. Noy 29-01-2003 Single Board 1 back end module controlling synchronisation and 4 front end modules

  16. Serial connection from BE I2C from BE Op-amp x6 DAC x6 3 channel analogue opto-tx Front End Virtex 2 Optical outputs SRAM - optional add on, 512kB x 36 @80MHz 3 channel analogue opto-tx To temp unit M. Noy 29-01-2003 Clock and Trigger from BE I2C from BE Single Front End Module 6 DAC  6 op-amp  2 analogue opto-tx-hybrid (current layout)

  17. M. Noy 29-01-2003 Summary The optical test board works, and will be used to test the FF1. Have a 9U crate, VME64x backplane, and 3.3v psu at IC. Software for the set up is functional, we can produce test vectors and sequence tests. Some work is required to make it more user-friendly. The next optical test card is being developed to provide multiple individually configurable channels, stepping towards more automation ( production testing)

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