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Impact of Parameter Variations on Multi-core chips E. Humenay, D. Tarjan, K. Skadron Department of Computer Science Un

Impact of Parameter Variations on Multi-core chips E. Humenay, D. Tarjan, K. Skadron Department of Computer Science University of Virginia. Motivation. Process variations are projected to severely impact the yield of high-performance semiconductors

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Impact of Parameter Variations on Multi-core chips E. Humenay, D. Tarjan, K. Skadron Department of Computer Science Un

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  1. Impact of Parameter Variations on Multi-core chips E. Humenay, D. Tarjan, K. Skadron Department of Computer Science University of Virginia

  2. Motivation • Process variations are projected to severely impact the yield of high-performance semiconductors • Multi-core architectures have become the future trend of high-performance chips • Understanding how process variations interact with CMPs is required

  3. Variation Types • PVT Variations • Process • Voltage • Temperature This work primarily focuses on process variations

  4. Process Variations • P variations stem from a variety of sources • Within-Die (WID) • Die-to-Die (D2D) • Wafer-to-Wafer (W2W) • Core-to-Core (C2C)

  5. WID Variations • WID variations can be further sub-divided • Systematic (WIDsys) • Random (WIDrand) • Threshold voltage, Vth, and effective channel length, Leff, are the 2 parameters most susceptible to random variations • Systematic Variations cause parameter values to be spatially correlated • Can be modeled as deterministic or random • WID variations cause C2C variations

  6. Drain Induced Barrier Lowering (DIBL) • Ideally, Vth and Leff values are independent of each other • The DIBL effect introduces a dependency • DIBL causes there to be an exponential dependency between Leff and sub-threshold leakage

  7. Modeling Methodology • In order to estimate the impact of P variations on delay it is necessary to have a critical path (CP) model • Prior CP models vary inputs into RC delay equation for Monte-Carlo analyses. • Simplicity comes at the expense of accuracy.

  8. CP Modeling: Prior Work • Fmax GCP model (Bowman, JSSC ‘02) • Ncp ~ Number of critical paths • Lcp ~Number of gates in critical path (Logic Depth) • Marculescu DAC ’05 • Ncp ~ stage’s device count. Ncp Lcp

  9. Importance of Ncp • As Ncp increases mean delay increases and delay variation decreases Ncp

  10. Modified CP Model • Goal: More accurately describe each functional unit’s delay distribution in order to determine which functional units will affect the final frequency distribution • Improvements • Considering wire delay when determining Lcp • Better Ncp assignments • Importance of Weff:

  11. Modified CP Model • Categorize each stage as being either SRAM or combinational logic • SRAM • L1s • TLBs • Register File • Rename Map • Issue Queue • Logic • Execution Units • Decode Stage • Issue Select

  12. SRAM model • Modified version of CACTI 4.0 is used to estimate fraction of access time susceptible to device variations • Ncp ~ number of read ports • Weff is dependent on unit type • L1 caches are assumed to be optimized for area (minimal sized Weff) • Time critical SRAM units have larger widths (Assume 5x larger than min) • Only consider variation in SRAM access time

  13. Combinational Logic Model • Logic model is based off of Sklansky adder • Delay modeled with Horowitz delay equation • Critical path is carry circuitry • Weff is chosen to alleviate fan-out delay

  14. WIDrand: SRAM delay • Because of large Ncp L1 is likely to be slowest SRAM unit • Nominal Frequency is 3GHz

  15. WIDrand: SRAM vs. Logic • L1 will also be slower than logic

  16. WIDsys Pattern • WIDsys model is derived from actual measurements (Friedberg ISQED’05) Fast, High-leakage Leff 28 POWER4-like core scaled to 45nm 27 14mm 26 Slow, Low-leakage 25 14mm

  17. Impact of WIDsys on Delay • WIDsys can cause frequency from core-to-core to differ by as much as 5% • Large Lcp value causes combinational logic units to be more affected by WIDsys variation

  18. Random Leakage Variation • WIDrand will not have an impact on leakage at the architectural level since total leakage is an aggregate sum Number of Transistors

  19. C2C Leakage Variation • Figure shows core leakage when considering all possible core locations on a die • 3 different magnitudes of DIBL are considered • BSIM suggests .15 (best-case)

  20. Conclusions • L1 caches will determine the WID mean frequency. Variations in other units will not directly affect the frequency distribution • Considering wire delay in CP model causes device variations to have less of an impact on the frequency distribution • WID variations do not result in significant C2C frequency differences • At 45nm, C2C sub-threshold leakage variation may be as much as 45%

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