1 / 10

Understanding the Chip Power and Cooling Scheme in Diamond Layer Models

Learn about the assumed material properties and cooling methods for a chip with digital and analog sections, plus the effects of temperature cooling at different distances.

tuyet
Télécharger la présentation

Understanding the Chip Power and Cooling Scheme in Diamond Layer Models

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. What is the Chip Power? Brian Maynard SU HEP GROUP 2-17-2010

  2. Assumed Material Properties

  3. 3 13 15 45 2 15

  4. Cooling Scheme For right now the cooling is applied in the model on top of a 5 mm thick layer of glue with k =1 W/mK at the outer perimeter of the diamond layer (~4 cm from edge of silicon)

  5. Including Digital Section of Chip 0.5 W/chip Analog +1/R section of chip (RDP) Constant digital section of chip (DPB) The orange part of the chip is situated such that it is farthest away from the beam center

  6. A Glimpse Across The Hole

  7. SummaryCooling at -35C Cooling applied from sides at 1.0cm from Silicon and from back at 1.5cm

More Related